ZHCSHE0 December 2017 TMS320F28377D-EP
|Supply ramp rate||VDDIO, VDD, VDDA, VDD3VFL, VDDOSC with respect to VSS||330||105||V/s|
The voltage on VDDIO should be greater than VDD or no less than 0.3 V below VDD at all times. VDDIO, VDD3VFL, VDDOSC, and VDDA should be powered up together and be kept within 0.3 V of each other during operation. Before powering the device, no voltage larger than 0.3 V above VDDIO should be applied to any digital pin, and no voltage larger than 0.3 V above VDDA should be applied to any analog pin. The VREFHI voltage should not exceed VDDA at any time.
An internal power-on-reset (POR) circuit holds the device in reset and keeps the I/Os in a high-impedance state during power up. External supply voltage supervisors (SVS) can be used to monitor the voltage on the 3.3-V and 1.2-V rails and drive XRS low should supplies fall outside operational specifications.