ZHCSNK4A October 2019 – February 2021 MSP430F5438A-ET
PRODUCTION DATA
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE | INTERRUPT FLAG | SYSTEM INTERRUPT | WORD ADDRESS | PRIORITY |
---|---|---|---|---|
System Reset Power-Up External Reset Watchdog Timeout, Password Violation Flash Memory Password Violation PMM Password Violation |
WDTIFG, KEYV (SYSRSTIV) (1) (2) | Reset | 0FFFEh | 63, highest |
System NMI PMM Vacant Memory Access JTAG Mailbox |
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV) (1) | (Non)maskable | 0FFFCh | 62 |
User NMI NMI Oscillator Fault Flash Memory Access Violation |
NMIIFG, OFIFG, ACCVIFG (SYSUNIV) (1) (2) | (Non)maskable | 0FFFAh | 61 |
TB0 | TBCCR0 CCIFG0 (3) | Maskable | 0FFF8h | 60 |
TB0 | TBCCR1 CCIFG1 to TBCCR6 CCIFG6, TBIFG (TBIV) (1) (3) |
Maskable | 0FFF6h | 59 |
Watchdog Timer_A Interval Timer Mode | WDTIFG | Maskable | 0FFF4h | 58 |
USCI_A0 Receive and Transmit | UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (3) | Maskable | 0FFF2h | 57 |
USCI_B0 Receive and Transmit | UCB0RXIFG, UCB0TXIFG (UCB0IV) (1) (3) | Maskable | 0FFF0h | 56 |
ADC12_A | ADC12IFG0 to ADC12IFG15 (ADC12IV) (1) (3) | Maskable | 0FFEEh | 55 |
TA0 | TA0CCR0 CCIFG0 (3) | Maskable | 0FFECh | 54 |
TA0 | TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4, TA0IFG (TA0IV) (1) (3) |
Maskable | 0FFEAh | 53 |
USCI_A2 Receive and Transmit | UCA2RXIFG, UCA2TXIFG (UCA2IV) (1) (3) | Maskable | 0FFE8h | 52 |
USCI_B2 Receive and Transmit | UCB2RXIFG, UCB2TXIFG (UCB2IV) (1) (3) | Maskable | 0FFE6h | 51 |
DMA | DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1) (3) | Maskable | 0FFE4h | 50 |
TA1 | TA1CCR0 CCIFG0 (3) | Maskable | 0FFE2h | 49 |
TA1 | TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2, TA1IFG (TA1IV) (1) (3) |
Maskable | 0FFE0h | 48 |
I/O Port P1 | P1IFG.0 to P1IFG.7 (P1IV) (1) (3) | Maskable | 0FFDEh | 47 |
USCI_A1 Receive and Transmit | UCA1RXIFG, UCA1TXIFG (UCA1IV) (1) (3) | Maskable | 0FFDCh | 46 |
USCI_B1 Receive and Transmit | UCB1RXIFG, UCB1TXIFG (UCB1IV) (1) (3) | Maskable | 0FFDAh | 45 |
USCI_A3 Receive and Transmit | UCA3RXIFG, UCA3TXIFG (UCA3IV) (1) (3) | Maskable | 0FFD8h | 44 |
USCI_B3 Receive and Transmit | UCB3RXIFG, UCB3TXIFG (UCB3IV) (1) (3) | Maskable | 0FFD6h | 43 |
I/O Port P2 | P2IFG.0 to P2IFG.7 (P2IV) (1) (3) | Maskable | 0FFD4h | 42 |
RTC_A | RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) (1) (3) | Maskable | 0FFD2h | 41 |
Reserved | Reserved (4) | 0FFD0h | 40 | |
⋮ | ⋮ | |||
0FF80h | 0, lowest |