ZHCSHX7B November   2017  – May 2022 DLPC120-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 LED Driver Interface
    2. 5.2 DMD Temperature Interface
    3.     General Purpose I/O
    4. 5.3 Main Video and Data Control Interface
    5. 5.4 DMD Interface
    6. 5.5 Memory Interface
    7.     Board Level Test and Debug
    8.     Manufacturing Test Support
    9.     Test Point Interface
    10.     Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics for I/O
    7. 6.7  Power Supply and Reset Timing Requirements
    8. 6.8  Reference Clock PLL Timing Requirements
    9. 6.9  Parallel Interface General Timing Requirements
    10. 6.10 Parallel Interface Frame Timing Requirements
    11. 6.11 Flash Memory Interface Timing Requirements
    12. 6.12 DMD Interface Timing Requirements
    13. 6.13 JTAG Interface Timing Requirements
    14. 6.14 I2C Interface Timing Requirements
  7. 7 Parameter Measurement Information
    1. 7.1 Parallel Interface Input Source Timing
    2. 7.2 Design for Test Functions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Flash Interface
      2. 8.3.2 Serial Flash Programming
      3. 8.3.3 DDR2 Memory Interface
      4. 8.3.4 JTAG and DMD Interface Test
      5. 8.3.5 Temperature Monitor Function
      6. 8.3.6 Host Command Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Video Mode
      2. 8.4.2 Splash Screen Mode
      3. 8.4.3 Test Pattern Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB layout guidelines for internal ASIC PLL power
      2. 11.1.2 DLPC120-Q1 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 PCB Routing Guidelines
      5. 11.1.5 Number of Layer Changes
      6. 11.1.6 Terminations
      7. 11.1.7 General Handling Guidelines for Unused CMOS-Type Pins
  12. 12Device and Documentation Support
    1. 12.1 第三方产品免责声明
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
        1. 12.2.1.1 Device Markings
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 接收文档更新通知
    5. 12.5 支持资源
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZXS|216
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.3 DDR2 Memory Interface

The DLPC120-Q1 ASIC DDR2 Memory interface consists of a 16-bit wide, 312-MHz (nominal) DDR2 interface with standard signaling.  The DLPC120-Q1 only support DDR2 interface with external termination.  The DDR2 interface is a very high speed signaling interface.

A DDR2 memory should be selected that supports the 312-MHz clock frequency and compliant to the JEDEC standard for DDR2 memories (JESD79-2A). 

Table 8-3 Compatible JEDEC DDR2 Devices
PARAMETERMINMAXUNITS
JEDEC DDR2 device speed grade(1)DDR2-800
JEDEC DDR2 device bit widthX16Bits
JEDEC DDR2 device count1Device(s)
JEDEC DDR2 Memory size5121024MByte
CAS Latency55
(1) The DDR2 interface operates with a clock frequency of 312 MHz, higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.
Table 8-4 DLPC120-Q1 Compatible DDR2 Device Options
VENDORPART NUMBERSIZEORGANIZATIONSPEED GRADECL
ISSIIS46DR16320C-25DBLA2512 Mb32Mx16DDR2-8005
MicronMT47H64M16HR-25E AAT1 Gb32Mx16DDR2-8005
MicronMT47H32M16HR-25E AAT512 Mb32Mx16DDR2-8005