SLUUDA0A April 2026 – July 2026 BQ27Z855
This command returns the PFStatus() flags on ManufacturerBlockAccess() or ManufacturerData().
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ISD HI | ISD LO | RSVD | TS | RSVD | DFW | PF FORCE | BSD | NTC | 2LVL | AFEC | AFER | FUSE | OCDL | DFE TF | CFE TF |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ASCDL | AOCCL | AOCDL | VIMA | VIMR | CD | IMP | CB | QIM | SOTF | COVL | SOT | SOCD | SOCC | SOV | SUV |
| ISD_HI (Bit 31): Internal short detection high failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| ISD_LO (Bit 30): Internal short detection low failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| RSVD (Bit 29): Reserved. Do not use. | ||
| TS (Bit 28): Open thermistor – TS1 failure. Triggered when the TS1 temperature reading falls significantly below the internal thermistor temperature for the configured time, indicating a disconnected or open thermistor. | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| RSVD (Bit 27): Reserved. Do not use. | ||
| DFW (Bit 26): Data flash wearout failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| PFFORCE (Bit 25): Permanent failure forced by command | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| BSD (Bit 24): Battery swelling detection failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| NTC (Bit 23): AFE NTC error | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| 2LVL (Bit 22): Second level protector failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| AFEC (Bit 21): AFE communication failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| AFER (Bit 20): AFE register failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| FUSE (Bit 19): Chemical fuse failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| OCDL (Bit 18): Overcurrent in discharge latch | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| DFETF (Bit 17): Discharge FET failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| CFETF (Bit 16): Charge FET failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| ASCDL (Bit 15): AFE short circuit in discharge latch | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| AOCCL (Bit 14): AFE overcurrent in charge latch | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| AOCDL (Bit 13): AFE overcurrent in discharge latch | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| VIMA (Bit 12): Voltage imbalance while pack is active failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| VIMR (Bit 11): Voltage imbalance while pack at rest failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| CD (Bit 10): Capacity degradation failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| IMP (Bit 9): Impedance failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| CB (Bit 8): Cell balancing failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| QIM (Bit 7): QMax imbalance failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| SOTF (Bit 6): Safety overtemperature FET failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| COVL (Bit 5): Cell overvoltage latch | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| SOT (Bit 4): Safety overtemperature cell failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| SOCD (Bit 3): Safety overcurrent in discharge | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| SOCC (Bit 2): Safety overcurrent in charge | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| SOV (Bit 1): Safety cell overvoltage failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |
| SUV (Bit 0): Safety cell undervoltage failure | ||
| 1 = | Detected | |
| 0 = | Not detected | |