ZHCSNJ7A April 2021 – February 2023 TDES954
PRODUCTION DATA
In the register definitions under the TYPE and DEFAULT heading, the following definitions apply:
The TDES954 implements the following register blocks, accessible via I2C as well as the bi-directional control channel:
ADDRESS RANGE | DESCRIPTION | ADDRESS MAP | |||
---|---|---|---|---|---|
0x00-0x31 | Digital Shared Registers | Shared | |||
0x32-0x3A | Digital CSI-2 Tx Port Registers | Shared | |||
0x3B - 0x4B | Reserved | Reserved | |||
0x4C-0x7F | Digital RX Port Registers (paged, broadcast write allowed) | V3LINK RX Port 0 R: 0x4C[5:4]=00 W: 0x4C[0]=1 | V3LINK RX Port 1 R: 0x4C[5:4]=01 W: 0x4C[1]=1 | ||
0x80-0xAF | Reserved | Reserved | |||
0xB0-0xB2 | Indirect Access Registers | Shared | |||
0xB0-0xBF | Digital Share Registers | Shared | |||
0xC0-0xCF | Reserved | Reserved | |||
0xD0-0xDF | Digital RX Port Test Mode Registers | V3LINK RX Port 0 | V3LINK RX Port 1 | ||
0xE0-0xEF | Reserved | Reserved | |||
0xF0-0xF5 | V3LINK RX ID | Shared | |||
0xF8-0xFB | Port I2C Addressing | Shared | |||
0xF6-0xF7 0xFC-0xFF | Reserved | Reserved |