ZHCSNJ7A April 2021 – February 2023 TDES954
PRODUCTION DATA
RX port specific register. The V3Link Port Select register 0x4C configures which unique RX port registers can be accessed by I2C read and write commands.
BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
---|---|---|---|---|
7:3 | RESERVED | R | 0x0 | Reserved |
2 | IE_V3LINK_ENC_ERR | R/W | 0x0 | Interrupt on V3Link Receiver Encoding Error When enabled, an interrupt is generated on detection of an encoding error on the V3Link interface for the receive port as reported in the V3LINK_ENC_ERROR bit in the RX_PORT_STS2 register |
1 | IE_BCC_SEQ_ERR | R/W | 0x0 | Interrupt on BCC SEQ Sequence Error. When enabled, an interrupt is generated if a Sequence Error is detected for the Bi-directional Control Channel forward channel receiver as reported in the BCC_SEQ_ERROR bit in the RX_PORT_STS1 register. |
0 | IE_BCC_CRC_ERR | R/W | 0x0 | Interrupt on BCC CRC error detect When enabled, an interrupt is generated if a CRC error is detected on a Bi-directional Control Channel frame received over the V3Link forward channel as reported in the BCC_CRC_ERROR bit in the RX_PORT_STS1 register. |