ZHCSNJ7A April 2021 – February 2023 TDES954
PRODUCTION DATA
RX port specific register. The V3Link Port Select register 0x4C configures which unique RX port registers can be accessed by I2C read and write commands.
BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
---|---|---|---|---|
7:6 | RAW10_8BIT_CTL | R/W | 0x0 | Raw10 8-bit mode When Raw10 Mode is enabled for the port, the input data is processed as 8-bit data and packed accordingly for transmission over CSI. 00 : Normal Raw10 Mode 01 : Reserved 10 : 8-bit processing using upper 8 bits. When selecting this value, change CSI data type value RAW10_DT in register 0x70[5:0] 11 : 8-bit processing using lower 8 bits. When selecting this value, change CSI data type value RAW10_DT in register 0x70[5:0] |
5 | DISCARD_ON _PAR_ERR | R/W | 0x1 | Discard frames on Parity Error 0 : Forward packets with parity errors 1 : Truncate Frames if a parity error is detected |
4 | DISCARD_ON _LINE_SIZE | R/W | 0x0 | Discard frames on Line Size 0 : Allow changes in Line Size within packets 1 : Truncate Frames if a change in line size is detected |
3 | DISCARD_ON _FRAME_SIZE | R/W | 0x0 | Discard frames on change in Frame Size When enabled, a change in the number of lines in a frame will result in truncation of the packet. The device will resume forwarding video frames based on the PASS_THRESHOLD setting in the PORT_PASS_CTL register. 0 : Allow changes in Frame Size 1 : Truncate Frames if a change in frame size is detected |
2 | RESERVED | R/W | 0x0 | Reserved |
1 | LV_POLARITY | R/W | 0x0 | LineValid Polarity This register indicates the expected polarity for the LineValid indication received in Raw mode. 1 : LineValid is low for the duration of the video line 0 : LineValid is high for the duration of the video line |
0 | FV_POLARITY | R/W | 0x0 | FrameValid Polarity This register indicates the expected polarity for the FrameValid indication received in Raw mode. 1 : FrameValid is low for the duration of the video frame 0 : FrameValid is high for the duration of the video frame |