ZHCSNJ7A April 2021 – February 2023 TDES954
PRODUCTION DATA
RX port specific register. The V3Link Port Select register 0x4C configures which unique RX port registers can be accessed by I2C read and write commands.
BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6 | IS_LINE_LEN_CHG | R | 0x0 | Video Line Length Interrupt Status A change in video line length has been detected. Status is reported in the LINE_LEN_CHG bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register. |
5 | IS_LINE_CNT_CHG | R | 0x0 | Video Line Count Interrupt Status A change in number of video lines per frame has been detected. Status is reported in the LINE_CNT_CHG bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register. |
4 | IS_BUFFER_ERR | R | 0x0 | Receiver Buffer Error Interrupt Status A Receive Buffer overflow has been detected as reported in the BUFFER_ERROR bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register. |
3 | IS_CSI_RX_ERR | R | 0x0 | CSI Receiver Error Interrupt Status The CSI Receiver has detected an error. CSI Receiver errors are reported in the CSI_RX_STS register (address 0x7A). This interrupt condition will be cleared by reading the CSI_RX_STS register. |
2 | IS_V3LINK_PAR_ERR | R | 0x0 | V3Link Receiver Parity Error Interrupt Status A parity error on the V3Link interface for the receive port has been detected. Parity error status is reported in the PARITY_ERROR bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register. |
1 | IS_PORT_PASS | R | 0x0 | Port Valid Interrupt Status A change in receiver port valid status as reported in the PORT_PASS bit in the PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register. |
0 | IS_LOCK_STS | R | 0x0 | Lock Interrupt Status A change in lock status has been detected. Status is reported in the LOCK_STS_CHG bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register. |