ZHCST39A December   2022  – September 2023 AFE11612-SEP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Characteristics
    7. 6.7  Timing Diagrams
    8. 6.8  Typical Characteristics: DAC
    9. 6.9  Typical Characteristics: ADC
    10. 6.10 Typical Characteristics: Internal Reference
    11. 6.11 Typical Characteristics: Temperature Sensor
    12. 6.12 Typical Characteristics: Digital Inputs
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Primary ADC Operation
        1. 7.3.1.1 Analog Inputs
          1. 7.3.1.1.1 Single-Ended Analog Input
          2. 7.3.1.1.2 Fully Differential Input
        2. 7.3.1.2 ADC Trigger Signals (See AFE configuration register 0 )
        3. 7.3.1.3 Double-Buffered ADC Data Registers
          1. 7.3.1.3.1 ADC Data Format
        4. 7.3.1.4 SCLK Clock Noise Reduction
        5. 7.3.1.5 Data Available Pin (DAV)
        6. 7.3.1.6 Convert Pin (CNVT)
        7. 7.3.1.7 Analog Input Out-of-Range Detection (See The Analog Input Out-of-Range Alarm Section)
        8. 7.3.1.8 Full-Scale Range of the Analog Input
      2. 7.3.2 Secondary ADC and Temperature Sensor Operation
        1. 7.3.2.1 Remote Sensing Diode
        2. 7.3.2.2 Ideality Factor
        3. 7.3.2.3 Filtering
        4. 7.3.2.4 Series Resistance Cancellation
        5. 7.3.2.5 Reading Temperature Data
        6. 7.3.2.6 Conversion Time
      3. 7.3.3 Reference Operation
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
      4. 7.3.4 DAC Operation
        1. 7.3.4.1 Resistor String
        2. 7.3.4.2 DAC Output
          1. 7.3.4.2.1 Full-Scale Output Range
          2. 7.3.4.2.2 DAC Output After Power-On Reset
        3. 7.3.4.3 Double-Buffered DAC Data Registers
        4. 7.3.4.4 Load DAC Latch
        5. 7.3.4.5 Synchronous Output Updating
        6. 7.3.4.6 Clear DACs
        7. 7.3.4.7 DAC Output Thermal Protection
      5. 7.3.5 Alarm Operation
        1. 7.3.5.1 Analog Input Out-of-Range Alarm
        2. 7.3.5.2 ALARM Pin
        3. 7.3.5.3 Hysteresis
        4. 7.3.5.4 False-Alarm Protection
      6. 7.3.6 General-Purpose Input and Output Pins (GPIO-0 To GPIO-7)
      7. 7.3.7 Device Reset Options
        1. 7.3.7.1 Hardware Reset
        2. 7.3.7.2 Software Reset
        3. 7.3.7.3 Power-On Reset (POR)
    4. 7.4 Device Functional Modes
      1. 7.4.1 DAC Output Mode
      2. 7.4.2 ADC Conversion Modes
        1. 7.4.2.1 Programmable Conversion Rate
        2. 7.4.2.2 Handshaking with the Host (See AFE configuration register 0 )
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 F/S-Mode Protocol
        2. 7.5.1.2 Hs-Mode Protocol
        3. 7.5.1.3 Address Pointer
        4. 7.5.1.4 Timeout Function
        5. 7.5.1.5 Device Communication Protocol For I2C
          1. 7.5.1.5.1 Writing A Single Register ( )
          2. 7.5.1.5.2 Writing Multiple Registers ( )
          3. 7.5.1.5.3 Reading a Single Register ( )
          4. 7.5.1.5.4 Reading Multiple Registers ( and )
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 SPI Shift Register
        2. 7.5.2.2 SPI Communications Command
        3. 7.5.2.3 Standalone Operation
        4. 7.5.2.4 Daisy-Chain Operation
    6. 7.6 Register Maps
      1. 7.6.1  Temperature Data Registers (Read-Only)
        1. 7.6.1.1 LT-Temperature-Data (LT_TEMP) Register (address = 00h) [reset = 0000h, 0°C]
        2. 7.6.1.2 D1-Temperature-Data (D1_TEMP) Register (address = 01h) [reset = 0000h, 0°C]
        3. 7.6.1.3 D2-Temperature-Data (D2_TEMP) Register (address = 02h) [reset = 0000h, 0°C]
      2. 7.6.2  Temperature Configuration (TEMP_CONFIG) Register (address = 0Ah) [reset = 003Ch or 3CFFh]
      3. 7.6.3  Temperature Conversion Rate (TEMP_CONV_RATE) Register (address = 0Bh) [reset = 0007h or 07FFh]
      4. 7.6.4  η-Factor Correction Registers: D1_N_ADJUST and D2_N_ADJUST (address = 21h and 22h) [reset = 0000h or 00FFh]
      5. 7.6.5  ADC-n-Data (ADC_n) Registers (addresses = 23h to 32h) [reset = 0000h]
      6. 7.6.6  DAC-n-Data (DAC_n) Registers (addresses = 33h to 3Eh) [reset = 0000h)
      7. 7.6.7  DAC-n-CLR-Setting (DAC_n_CLR) Registers (addresses = 3Fh to 4Ah) [reset = 0000h]
      8. 7.6.8  GPIO Register (address = 4Bh) [reset = 00FFh]
      9. 7.6.9  AFE Configuration Register 0 (AFE_CONFIG_0) (address = 4Ch) [reset = 2000h]
      10. 7.6.10 AFE Configuration Register 1 (AFE_CONFIG_1) (Address = 4Dh) [reset = 0070h]
      11. 7.6.11 Alarm Control Register (ALR_CTRL) (address = 4Eh) [reset = 0000h]
      12. 7.6.12 STATUS Register (Address = 4Fh) [reset = 0000h]
      13. 7.6.13 ADC Channel Register 0 (ADC_CH0) (address = 50h) [reset = 0000h]
      14. 7.6.14 ADC Channel Register 1 (ADC_CH1) (address = 51h) [reset = 0000h]
      15. 7.6.15 ADC Gain Register (ADC_GAIN) (address = 52h) [reset = FFFFh]
      16. 7.6.16 AUTO_DAC_CLR_SOURCE Register (address = 53h) [reset = 0004h]
      17. 7.6.17 AUTO_DAC_CLR_EN Register (address = 54h) [reset = 0000h]
      18. 7.6.18 SW_DAC_CLR Register (address = 55h) [reset = 0000h]
      19. 7.6.19 HW_DAC_CLR_EN_0 Register (address = 56h) [reset = 0000h]
      20. 7.6.20 HW_DAC_CLR_EN_1 Register (address = 57h) [reset = 0000h]
      21. 7.6.21 DAC Configuration (DAC_CONFIG) Register (address = 58h) [reset = 0000h]
      22. 7.6.22 DAC Gain (DAC_GAIN) Register (address = 59h) [reset = 0000h]
      23. 7.6.23 Analog Input Channel Threshold Registers (addresses = 5Ah To 61h)
        1. 7.6.23.1 Input-n-High-Threshold Register (where n = 0, 1, 2, 3; addresses: 0 = 5Ah, 1 = 5Ch, 2 = 5Eh, 3 = 60h) [reset = 0FFFh]
        2. 7.6.23.2 Input-n-Low-Threshold Register (where n = 0, 1, 2, 3; addresses: 0 = 5Bh, 1 = 5Dh, 2 = 5Fh, 3 = 61h) (reset = 0000h)
      24. 7.6.24 Temperature Threshold Registers
        1. 7.6.24.1 LT_HIGH_THRESHOLD Register (address = 62h) [reset = 07FFh, +255.875°C]
        2. 7.6.24.2 LT_LOW_THRESHOLD Register (address = 63h) [reset = 0800h, –256°C]
        3. 7.6.24.3 D1_HIGH_THRESHOLD Register (address = 64h) [reset = 07FFh, +255.875°C]
        4. 7.6.24.4 D1_LOW_THRESHOLD Register (address = 65h) [reset = 0800h, –256°C]
        5. 7.6.24.5 D2_HIGH_THRESHOLD Register (address = 66h) [reset = 07FFh, +255.875°C]
        6. 7.6.24.6 D2_LOW_THRESHOLD Register (address = 67h) [reset = 0800h, –256°C]
      25. 7.6.25 Hysteresis Registers
        1. 7.6.25.1 Hysteresis Register 0 (HYST_0) (address = 68h) [reset = 0810h, 8 LSB]
        2. 7.6.25.2 Hysteresis Register 1 (HYST_1) (address = 69h) [reset = 0810h, 8 LSB]
        3. 7.6.25.3 Hysteresis Register 2 (HYST_2) (address = 6Ah) [reset = 2108h, 8°C]
      26. 7.6.26 Power-Down Register (PWR_DOWN) (address = 6Bh) [reset = 0000h)
      27. 7.6.27 Device ID Register (DEVICE_ID) (read only address = 6Ch) [reset = 1220h]
      28. 7.6.28 Software Reset (SW_RST) Register (read or write address = 7Ch) [reset = N/A)
        1. 7.6.28.1 SPI Mode
        2. 7.6.28.2 I2C Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sequencing
        2. 8.2.2.2 Negative GaN Biasing
        3. 8.2.2.3 VDRAIN Monitoring
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Supply Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Diagram
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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7.3.4.6 Clear DACs

DAC-n can be cleared with hardware or software, as shown in Figure 7-11. When DAC-n goes to a clear state, DAC-n is immediately loaded with predefined code in the DAC-n-CLR-setting register, and the output is set to the corresponding level to shut down the external LDMOS device. However, the DAC-n-data register does not change. When the DAC goes back to normal operation, DAC-n is immediately loaded with the previous data from the DAC-n-data register and the output of DACn-OUT is set back to the previous level to restore LDMOS to the status before shutdown, regardless of the SLDAC-n bit status.

GUID-DEEEAB86-BACF-4EBA-9E1B-73012C41FD67-low.gifFigure 7-11 Clearing DAC-n

The device is implemented with two external control lines, the DAC-CLR-0 and DAC-CLR-1 pins, to clear the DACs. When either pin goes low, the corresponding user-selected DACs are in a cleared state. The HW_DAC-CLR-0 register determines which DAC is cleared when the DAC-CLR-0 pin is low. The register contains 12 clear bits (CLR-n), one per DAC. If the CLR-n bit is 1, DAC-n is in a cleared state when the DAC-CLR-0 pin is low. However, if the CLR-n bit is 0, DAC-n does not change when the pin is low. Likewise, the HW-DAC-CLR-1 register determines which DAC is cleared when the DAC-CLR-1 pin is low.

Writing directly to the SW_DAC_CLR register puts the selected DACs in a cleared state. DACs can also be forced into a clear state by alarm events. The AUTO-DAC-CLR-SOURCE register specifies which alarm events force the DACs into a clear state, and the AUTO-DAC-CLR-EN register defines which DACs are forced into a clear state. Refer to the AUTO-DAC-CLR-SOURCE register and AUTO-DAC-CLR-EN register for further details.