ZHCST39A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | SLDA [11:0] | ||||||||||||||
R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
11-0 | SLDA | R/W | 0h | DAC synchronous load enable bit. 0: Reserved for DACs not being updated. The synchronous load DAC signal (ILDAC) does not affect DACn. The default value of SLDA-n is 0. 1: Synchronous load must be enabled for proper DAC operation. When internal load DAC signal ILDAC occurs, the DAC-n latch is loaded with the value of the corresponding DACn-data register, and the output of DAC-n updates immediately. The internal load DAC signal ILDAC is generated by writing a 1 to the ILDAC bit in the AFE configuration register. A write command to the DAC-n-data register updates that register only, and does not change the DAC-n output. Any DAC channels that are not accessed are not reloaded. |
The DACs can be forced to a clear state immediately by the external DAC-CLR-n signal, by alarm events, and by writing to the SW-DAC-CLR register. In these cases, the SLDA-n bit is ignored.