SPRADE8 November   2023 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   EEPROM Emulation for Generation 3 C2000 Real Time Controllers
  2.   Trademarks
  3. 1 Introduction
  4. 2 Difference Between EEPROM and On-Chip Flash
  5. 3 Overview
    1. 3.1 Basic Concept
    2. 3.2 Single-Unit Method
    3. 3.3 Ping-Pong Method
    4. 3.4 Creating EEPROM Sections (Pages) and Page Identification
  6. 4 Software Description
    1. 4.1 Software Functionality and Flow
  7. 5 Ping-Pong Emulation
    1. 5.1 User-Configuration
      1. 5.1.1 EEPROM_Config.h
      2. 5.1.2 F28P65x_EEPROM.c
    2. 5.2 EEPROM Functions
      1. 5.2.1  EEPROM_Config_Check
      2. 5.2.2  Configure_Protection_Masks
      3. 5.2.3  EEPROM_Write
      4. 5.2.4  EEPROM_Read
      5. 5.2.5  EEPROM_Erase
        1. 5.2.5.1 Erase_Bank
      6. 5.2.6  EEPROM_GetValidBank
      7. 5.2.7  EEPROM_UpdateBankStatus
      8. 5.2.8  EEPROM_UpdatePageStatus
      9. 5.2.9  EEPROM_Get_64_Bit_Data_Address
      10. 5.2.10 EEPROM_Program_64_Bits
      11. 5.2.11 EEPROM_CheckStatus
      12. 5.2.12 ClearFSMStatus
    3. 5.3 Testing Example
  8. 6 Single-Unit Emulation
    1. 6.1 User-Configuration
      1. 6.1.1 EEPROM_Config.h
      2. 6.1.2 F28P65x_EEPROM.c
    2. 6.2 EEPROM Functions
      1. 6.2.1  EEPROM_Config_Check
      2. 6.2.2  Configure_Protection_Masks
      3. 6.2.3  EEPROM_Write
      4. 6.2.4  EEPROM_Erase
      5. 6.2.5  EEPROM_GetValidBank
      6. 6.2.6  EEPROM_Get_64_Bit_Data_Address
      7. 6.2.7  EEPROM_UpdateBankStatus
      8. 6.2.8  EEPROM_UpdatePageStatus
      9. 6.2.9  EEPROM_Get_64_Bit_Data_Address
      10. 6.2.10 EEPROM_Program_64_Bits
      11. 6.2.11 EEPROM_CheckStatus
      12. 6.2.12 ClearFSMStatus
    3. 6.3 Testing Example
  9. 7 Application Integration
  10. 8 Adapting to Other Gen 3 C2000 MCUs
  11. 9 Flash API
    1. 9.1 Flash API Checklist
      1. 9.1.1 Flash API Do's and Do Not's
  12. 10Source File Listing
  13. 11Conclusion
  14. 12References

3.4 Creating EEPROM Sections (Pages) and Page Identification

In order to support EEPROM emulation with varying data sizes (other than 64-bits), the Flash Sectors selected for emulation are divided into a format referred to as EEPROM Banks (not to be confused with Flash Banks) and Pages. First, the Flash sector (or set of chosen Flash Sectors) is divided into EEPROM banks. Each EEPROM bank is further divided into Pages. This partitioning is shown in Bank Partitioning. The partitioning of EEPROM Banks and Pages is the same for Single-Unit and Ping-Pong emulation.

Using this format allows the application to:

  • Read back the data from the page written during the previous save
  • Write the latest data to a new page
  • Read from any previously stored data, if required by the application
GUID-20231004-SS0I-JTKD-2S3T-DKFJDSLT4WZ2-low.png Figure 3-3 Bank Partitioning

The first eight 16-bit words of each EEPROM bank are reserved for EEPROM bank status information and the first eight words of each page are reserved for page status information. Every time a new set of data is written to a page, the status location of the last page and the next page are modified. When a new EEPROM bank is used the Bank Status of the last and current EEPROM banks are updated. Both the EEPROM Bank and Page status words differentiate between the current EEPROM Bank/Page and a used EEPROM Bank/Page in the same way. To mark an EEPROM Bank or Page as current, the first 64-bits are written with the appropriate status code. To mark an EEPROM Bank or Page as full, the latter 64-bits are written with the appropriate status code. More details about the status codes can be found in the EEPROM_GetValidBank.

As seen in Page Layout, all pages contain an eight-word page status and a configurable amount of data space. Page 0 is slightly different as it contains the EEPROM bank status as well. Only Pages 0 and 1 are shown, but it should be noted that Page 2 through Page (N-1) are identical to Page 1.

GUID-20231004-SS0I-MMG4-PHZM-BM0NHPRC0DGB-low.png Figure 3-4 Page Layout