SPRACF0D May   2018  – April 2026 F28377D-SEP , TMS320C28341 , TMS320C28342 , TMS320C28343 , TMS320C28343-Q1 , TMS320C28344 , TMS320C28345 , TMS320C28346 , TMS320C28346-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F2802-Q1 , TMS320F28020 , TMS320F28021 , TMS320F28022 , TMS320F28022-Q1 , TMS320F28023 , TMS320F28023-Q1 , TMS320F28026 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027 , TMS320F28027-Q1 , TMS320F28027F , TMS320F28027F-Q1 , TMS320F28030 , TMS320F28030-Q1 , TMS320F28031 , TMS320F28031-Q1 , TMS320F28032 , TMS320F28032-Q1 , TMS320F28033 , TMS320F28033-Q1 , TMS320F28034 , TMS320F28034-Q1 , TMS320F28035 , TMS320F28035-Q1 , TMS320F28050 , TMS320F28051 , TMS320F28052 , TMS320F28052-Q1 , TMS320F28052F , TMS320F28052F-Q1 , TMS320F28052M , TMS320F28052M-Q1 , TMS320F28053 , TMS320F28054 , TMS320F28054-Q1 , TMS320F28054F , TMS320F28054F-Q1 , TMS320F28054M , TMS320F28054M-Q1 , TMS320F28055 , TMS320F2806-Q1 , TMS320F28062 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28066-Q1 , TMS320F28067 , TMS320F28067-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28232 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335 , TMS320F28335-Q1 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 What Is JTAG?
  5. 2 Common JTAG Debug Probes
  6. 3 Debug Steps for LaunchPad™ Development Kits and controlCARDs
    1. 3.1 LaunchPad™ Development Kits
    2. 3.2 controlCARDs
  7. 4 Common Error Codes
    1. 4.1 Common Error Codes
  8. 5 Multiple Devices in JTAG Chain
  9. 6 Non-Intrusive Debug
  10. 7 Disabling and Resetting the JTAG TAP
  11. 8 JTAG Connectivity Debug Flows
    1. 8.1 Overall Debug Flow
    2. 8.2 High-Voltage Isolation Check Flow
    3. 8.3 Main JTAG Debug Flow
  12. 9 Detailed Flow Step Information
    1. 9.1 Isolation Pre-Check Flow
    2. 9.2 JTAG Debug Flow
  13. 10References
  14. 11Revision History

7 Disabling and Resetting the JTAG TAP

Note:

The following section is relevant to the following device families:

  • F28004x
  • F28002x
  • F28003x
  • F280013x
  • F280015x
  • F28P55x
  • F28P65x
  • F28E12x

The JTAG Test Access Port (TAP) is a standardized hardware interface (IEEE 1149.1) used for accessing, testing, and debugging the on-chip logic. The TAP acts as a FSM that shifts data in/out through TDI/TDO to control boundary scan registers for board-level testing, hardware debugging, and system programming.

The TAP_STATUS register reflects the status of the TAP at any given time. Normally when no JTAG emulator is connected to the device, the state is held in the TLR (Test Logic Reset) state. In some cases with excessive PCB noise, there can be unwanted TMS and TCK toggles that take JTAG out of the TLR state. When persistent, this can ultimately lead to unwanted activation of the JTAG Boundary Scan or some other JTAG mode that can directly interfere with the intended application. The TAP can potentially control the GPIOs by bypassing normal application logic through boundary scan (BSCAN) mode, which can ultimately cause the system to hang.

Figure 7-1 TAP_STATUS Register
3130292827262524
DCONRESERVED
R-0hR-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
TAP_STATE
R-0h
76543210
TAP_STATE
R-0h
Table 7-1 TAP_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31DCONR0hDebugConnect indication from IcePick.

Reset type: PORESETn

30-16RESERVEDR-00hReserved
15-0TAP_STATER0hTAP State Vector. With bits representing, Connect coresponding POTAP* output to the
0x0001:TLR,
0x0002:IDLE,
0x0004:SELECTDR,
0x0008:CAPDR,
0x0010:SHIFTDR,
0x0020:EXIT1DR,
0x0040:PAUSEDR,
0x0080:EXIT2DR,
0x0100:UPDTDR,
0x0200:SLECTIR,
0x0400:CAPIR,
0x0800:SHIFTIR,
0x1000:EXIT1IR,
0x2000:PAUSEIR,
0x4000:EXIT2IR,
0x8000:UPDTIR

Reset type: PORESETn

Table 7-2 lists the various BSCAN tests implemented on C2000 devices. These modes can be referenced in the BSDL models provided for each device family on the TI product page. Not all of the BSCAN modes gates GPIO function. The scan sequence 'xxxxxx' represents a binary input on TDI that ultimately places the device in the corresponding BSCAN mode once the final bit is clocked by TCK.

Table 7-2 Boundary Scan Modes
Instruction TDI Serial Scan GPIO Impact System Impact
EXTEST 'b011000 Gates GPIOs (Configurable) Possible
SAMPLE 'b011011 None None
BYPASS 'b111111 None None
HIGHZ 'b011110 Gates GPIOs All pins disconnected
IDCODE 'b000100 None None
PRELOAD 'b011011 None None

To avoid any unintentional BSCAN modes from being entered, place strong enough external pull resistors (particularly on TMS and TCK) on the board to prevent noise from activating JTAG. For maximum reliability, if TDI is unused in the system, change the GPIO direction to be an output and drive low. Since 'b000000 is an unused instruction scan sequence, this won't change the device behavior when scanned in.

Note: On F28P55x and F28P65x devices, the TAP_CONTROL register is provided to disable BSCAN mode entirely by setting the BSCAN_DIS bit. Debugger access through the JTAG is still allowed even if BSCAN mode is disabled.

From a software perspective, the TAP_STATUS register can be polled by the application code to detect device disturbance. The SOFTPRES40[JTAG_nTRST] register can also be used to reset the JTAG TAP through software. Users can detect the TAP transitioning from the TLR to the IDLE state (which doesn't impact the system yet), and reset the TAP back to the TLR state before the device issues an unknown instruction. Please refer to this E2E FAQ for details on how to use SOFTPRES40 to reset the JTAG TAP state, even when the register is undocumented in CCS or the device-specific Technical Reference Manual.

Note: Use the SOFTPRES40 register with caution, as this prevents connecting a debugger unless the code qualifies writes to this register with some other GPIO state or other means to distinguish between noise and debugger accesses. For example, the DCON bit in the TAP_STATUS register can be used to indicate if there is a debugger connected to the device.