SLVUBY7A October   2020  – October 2022 DRA821U , LP8764-Q1 , TPS6594-Q1

 

  1.   User's Guide for Powering DRA821 with TPS6594-Q1 and LP8764-Q1
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States: ACTIVE, MCU, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 GPIO8 and Watchdog
  10. 8Additional Resources
  11. 9Revision History

5.10 Miscellaneous Settings

These settings detail the default configurations of additional settings, such as spread spectrum, BUCK frequency, and LDO timeout. All these settings can be changed though I2C after startup.

Table 5-11 Miscellaneous NVM Settings
Register Name Field Name TPS6594141B-Q1 LP876441B1-Q1
Value Description Value Description
PLL_CTRL EXT_CLK_FREQ 0x1 2.2 MHz 0x0 1.1 MHz
CONFIG_1 TWARN_LEVEL 0x0 130C 0x0 130C
TSD_ORD_LEVEL 0x0 140C 0x0 140C
I2C1_HS 0x0 Standard, fast or fast+ by default, can be HS-mode by HS-mode controller code. 0x0 Standard, fast or fast+ by default, can be HS-mode by HS-mode controller code.
I2C2_HS 0x0 Standard, fast or fast+ by default, can be HS-mode by HS-mode controller code. 0x0 Standard, fast or fast+ by default, can be HS-mode by HS-mode controller code.
EN_ILIM_FSM_CTRL 0x0 Buck/LDO regulators ILIM interrupts do not affect FSM triggers. 0x0 Buck regulators ILIM interrupts do not affect FSM triggers.
NSLEEP1_MASK 0x0 NSLEEP1(B) affects FSM state transitions. 0x1 NSLEEP1(B) does not affect FSM state transitions.
NSLEEP2_MASK 0x0 NSLEEP2(B) affects FSM state transitions. 0x1 NSLEEP2(B) does not affect FSM state transitions.
CONFIG_2 BB_CHARGER_EN 0x0 Disabled
BB_VEOC 0x0 2.5V
BB_ICHR 0x0 100uA
RECOV_CNT_REG_2 RECOV_CNT_THR 0xf 0xf 0xf 0xf
BUCK_RESET_REG BUCK1_RESET 0x0 0x0 0x0 0x0
BUCK2_RESET 0x0 0x0 0x0 0x0
BUCK3_RESET 0x0 0x0 0x0 0x0
BUCK4_RESET 0x0 0x0 0x0 0x0
BUCK5_RESET 0x0 0x0
SPREAD_SPECTRUM_1 SS_EN 0x0 Spread spectrum disabled 0x0 Spread spectrum disabled
SS_MODE 0x1 Mixed dwell 0x1 Mixed dwell
SS_DEPTH 0x0 No modulation 0x0 No modulation
SPREAD_SPECTRUM_2 SS_PARAM1 0x7 0x7 0x7 0x7
SS_PARAM2 0xc 0xc 0xc 0xc
FREQ_SEL BUCK1_FREQ_SEL 0x1 4.4 MHz 0x1 4.4 MHz
BUCK2_FREQ_SEL 0x1 4.4 MHz 0x1 4.4 MHz
BUCK3_FREQ_SEL 0x1 4.4 MHz 0x1 4.4 MHz
BUCK4_FREQ_SEL 0x1 4.4 MHz 0x1 4.4 MHz
BUCK5_FREQ_SEL 0x1 4.4 MHz
FSM_STEP_SIZE PFSM_DELAY_STEP 0xb 0xb 0xb 0xb
LDO_RV_TIMEOUT_ REG_1 LDO1_RV_TIMEOUT 0xf 16ms
LDO2_RV_TIMEOUT 0xf 16ms
LDO_RV_TIMEOUT_ REG_2 LDO3_RV_TIMEOUT 0xf 16ms
LDO4_RV_TIMEOUT 0xf 16ms
USER_SPARE_REGS USER_SPARE_1 0x0 0x0 0x0 0x0
USER_SPARE_2 0x0 0x0 0x0 0x0
USER_SPARE_3 0x0 0x0 0x0 0x0
USER_SPARE_4 0x0 0x0 0x0 0x0
ESM_MCU_MODE_ CFG ESM_MCU_EN 0x0 ESM_MCU disabled. 0x0 ESM_MCU disabled.
ESM_SOC_MODE_ CFG ESM_SOC_EN 0x0 ESM_SoC disabled.
RTC_CTRL_2 XTAL_EN 0x1 Crystal oscillator is enabled
LP_STANDBY_SEL 0x0 LDOINT is enabled in standby state. 0x0 Normal standby state is used.
FAST_BIST 0x0 Logic and analog BIST is run at BOOT BIST. 0x0 Logic and analog BIST is run at BOOT BIST.
STARTUP_DEST 0x3 ACTIVE 0x3 ACTIVE
XTAL_SEL 0x1 9 pF
PFSM_DELAY_REG_1 PFSM_DELAY1 0x54 0x54