SLVUBY7A October   2020  – October 2022 DRA821U , LP8764-Q1 , TPS6594-Q1

 

  1.   User's Guide for Powering DRA821 with TPS6594-Q1 and LP8764-Q1
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States: ACTIVE, MCU, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 GPIO8 and Watchdog
  10. 8Additional Resources
  11. 9Revision History

6.3.7 TO_MCU

The TO_MCU sequence first turns off rails and GPIOs which are assigned to the SOC power group. The sequence enables the MCU rails, in the event that they are not already active (when transitioning from STANDBY to MCU_ONLY for example). If the I2C_6 bit (FSM_I2C_TRIGGERS register) is set high in both PMICs, the PMICs retain the processor GPIOs while keeping the MCU active as shown in Figure 6-9. If the I2C_7 bit (FSM_I2C_TRIGGERS register) is set high in both PMICs, they retain the SRAM while keeping the MCU active as shown in Figure 6-10. If both bits are set high in both devices, both GPIO and DDR rails are retained while the MCU is active, as shown in Figure 6-11. Lastly, if both I2C_6 and I2C_7 are set low in both devices, only the MCU rails remain active in this state as shown in Figure 6-12. These bits need to be set by I2C in both PMICs before a trigger for the retention state occurs.

Similar to the TO_ACTIVE sequence, the nRSTOUT signal is delayed 9ms after TPS65941B BUCK3 regulator is enabled by default. This delay is always 500us plus the time set by the PFSM_DELAY1 register. This value can be changed before entering the retention state to control when the nRSTOUT pin is released.

Figure 6-9 TO_MCU Sequence with I2C_6 = 1 and I2C7 = 0 in both PMICs
Figure 6-10 TO_MCU Sequence with I2C_6 = 0 and I2C_7 = 1 in both PMICs
Figure 6-11 TO_MCU Sequence with I2C6 = 1 and I2C_7 = 1 in both PMICs
Figure 6-12 TO_MCU Sequence with I2C6 = 0 and I2C_7 = 0 in both PMICs