SLVUBY7A October   2020  – October 2022 DRA821U , LP8764-Q1 , TPS6594-Q1

 

  1.   User's Guide for Powering DRA821 with TPS6594-Q1 and LP8764-Q1
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States: ACTIVE, MCU, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 GPIO8 and Watchdog
  10. 8Additional Resources
  11. 9Revision History

7.1.3 RETENTION

As shown in Section 6.3.9, the MCU is powered off and therefore the transition out of the RETENTION to the MCU ONLY or the ACTIVE states must be configured before entering RETENTION. Similar to the MCU ONLY state the I2C_6 and I2C_7 triggers must be set for both PMICs. Below is an example of entering GPIO RETENTION (I2C_6=1) and using TPS6594141B GPIO4 to wake the PMICs into the ACTIVE state.

Write 0x48:0x85:0x40:0x7F    //I2C_6 is high
Write 0x4C:0x85:0x40:0x7F
Write 0x48:0x34:0xC0:0x3F    //Set GPIO4 to WKUP1 (goes to ACTIVE state)
Write 0x48:0x64:0x08:0xF7    //clear interrupt for GPIO4 falling edge
Write 0x48:0x4F:0x00:0xF7    //unmask interrupt for GPIO4 falling edge
Write 0x48:0x86:0x00:0xFC    //trigger the TO_RETENTION power sequence
After the GPIO4 has gone low the the PMICs have returned to the ACTIVE state
Write 0x48:0x86:0x03:0xFC    //Set NSLEEPx bits for ACTIVE state
Write 0x48:0x64:0x08:0xF7    //clear interrupt of GPIO4

Below is example of entering DDR RETENTION (I2C_7 = 1) and using the TPS6594141B RTC Timer to wake the PMICs into the ACTIVE state.

Write 0x48:0x85:0x80:0x7F     // I2C_7 is high
Write 0x4C:0x85:0x80:0x7F
Write 0x48:0xC3:0x01;0xFE     // Enable Crystal
Write 0x48:0xC5:0x05:0xF8     // minute timer, enable TIMER interrupts
Write 0x48:0xC2:0x01:0xFE     // start timer, if the timer values are non-zero clear before starting
Write 0x4C:0x3D:0x06:0xF9     // set PMICB:GPIO2 and GPIO3
Write 0x48:0x86:0x00:0xFC     // trigger the TO_RETENTION power sequence
After the RTC Timer interrupt has occurred and the PMICs have returned to the ACTIVE state
Write 0x48:0x86:0x03:0xFC     // Set NSLEEPx bits for ACTIVE state
Write 0x48:0xC5:0x00:0xFB     // disable timer interrupt, clear bit 2
Write 0x48:0xC4:0x00:0xDF     // clear timer interrupt, clear bit 5
Write 0x4C:0x3D:0x00:0xF7     // clear PMICB:GPIO2 and GPIO3