SLLA651 April   2025 TCAN2845-Q1 , TCAN2847-Q1 , TCAN2855-Q1 , TCAN2857-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Device States
    1. 2.1 Init Mode
    2. 2.2 Restart Mode
    3. 2.3 Standby Mode
    4. 2.4 Normal Mode
    5. 2.5 Sleep Mode
    6. 2.6 Fail-Safe Mode
  6. 3Power Electronics
    1. 3.1 VSUP
    2. 3.2 VHSS
    3. 3.3 VCAN
    4. 3.4 VCC1
    5. 3.5 VCC2
    6. 3.6 VEXMON, VEXCTRL, and VEXCC
    7. 3.7 HSSx
  7. 4Communication Capabilities
    1. 4.1 CAN-FD and Classical CAN
    2. 4.2 CAN-SIC
    3. 4.3 LIN
  8. 5Protection Features
    1. 5.1 Undervoltage (UV) Monitors
      1. 5.1.1 VSUP
      2. 5.1.2 VHSS
      3. 5.1.3 VCAN
      4. 5.1.4 VEXCC
      5. 5.1.5 VCC1
      6. 5.1.6 VCC2
    2. 5.2 Overvoltage (OV) Monitors
      1. 5.2.1 HSSx
      2. 5.2.2 VCC1
      3. 5.2.3 VCC2
      4. 5.2.4 VEXCC
    3. 5.3 Short Circuit (SC) Monitors
      1. 5.3.1 VCC1
      2. 5.3.2 VCC2
      3. 5.3.3 VEXCC
    4. 5.4 Electrical Faults and Impact on SBC Mode
    5. 5.5 Temperature Sensors
    6. 5.6 Watchdog
      1. 5.6.1 Watchdog Error Counter
      2. 5.6.2 Timeout
      3. 5.6.3 Window
      4. 5.6.4 Initial Long Window
      5. 5.6.5 Q&A
    7. 5.7 Communication Fault Monitoring
      1. 5.7.1 CAN
      2. 5.7.2 LIN
    8. 5.8 LIMP
  9. 6Programming, Memory, and Control
    1. 6.1 SPI
    2. 6.2 EEPROM
    3. 6.3 Interrupts
    4. 6.4 Control
  10. 7Miscellaneous Features
    1. 7.1 Local Wake Ups
    2. 7.2 CAN Bus Wake Up (BWRR)
    3. 7.3 Partial Networking
    4. 7.4 GFO, nRST, and SW
  11. 8Summary
  12. 9References

6.2 EEPROM

The TCAN28xx line of devices also includes an EEPROM that serves 2 main purposes. The first purpose is that this contains trimming information for device operation – this portion of the EEPROM is not accessible to end user. The second use is to save a partial configuration using an EEPROM save – the following bits are saved within the TCAN28xx line of devices.

Table 6-1 Registers and Bits That can be Stored in EEPROM
Register ID Register Address Bits Saved
SPI_CONFIG 9h 0-3
SBC_CONFIG Ch 0-1,4,6
VREG_CONFIG1 Dh 0-7
SBC_CONFIG1 Eh 0,3-5,7
WAKE_PIN_CONFIG1 11h 0-4
WAKE_PIN_CONFIG2 12h 0-1,5,6
WD_CONFIG_1 13h 0-7
WD_CONFIG_2 14h 0,5-7
WD_RST_PULSE 16h 4-7
DEVICE_CONFIG1 1Ah 0,4,7
DEVICE_CONFIG2 1Bh 0
SWE_TIMER 1Ch 3-7
nRST_CNTL 29h 5
WAKE_PIN_CONFIG4 2Bh 0-1,3,4-5,7
WD_QA_CONFIG 2Dh 0-7
HSS_CNTL3 4Fh 0,4

To save a partial configuration to the EEPROM one-byte transactions with CRC must be enabled. If the companion controller chosen does not support CRC bytes, please see table 8-26 in data sheet for process to save to EEPROM without CRC capable controller.