SLLA651 April   2025 TCAN2845-Q1 , TCAN2847-Q1 , TCAN2855-Q1 , TCAN2857-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Device States
    1. 2.1 Init Mode
    2. 2.2 Restart Mode
    3. 2.3 Standby Mode
    4. 2.4 Normal Mode
    5. 2.5 Sleep Mode
    6. 2.6 Fail-Safe Mode
  6. 3Power Electronics
    1. 3.1 VSUP
    2. 3.2 VHSS
    3. 3.3 VCAN
    4. 3.4 VCC1
    5. 3.5 VCC2
    6. 3.6 VEXMON, VEXCTRL, and VEXCC
    7. 3.7 HSSx
  7. 4Communication Capabilities
    1. 4.1 CAN-FD and Classical CAN
    2. 4.2 CAN-SIC
    3. 4.3 LIN
  8. 5Protection Features
    1. 5.1 Undervoltage (UV) Monitors
      1. 5.1.1 VSUP
      2. 5.1.2 VHSS
      3. 5.1.3 VCAN
      4. 5.1.4 VEXCC
      5. 5.1.5 VCC1
      6. 5.1.6 VCC2
    2. 5.2 Overvoltage (OV) Monitors
      1. 5.2.1 HSSx
      2. 5.2.2 VCC1
      3. 5.2.3 VCC2
      4. 5.2.4 VEXCC
    3. 5.3 Short Circuit (SC) Monitors
      1. 5.3.1 VCC1
      2. 5.3.2 VCC2
      3. 5.3.3 VEXCC
    4. 5.4 Electrical Faults and Impact on SBC Mode
    5. 5.5 Temperature Sensors
    6. 5.6 Watchdog
      1. 5.6.1 Watchdog Error Counter
      2. 5.6.2 Timeout
      3. 5.6.3 Window
      4. 5.6.4 Initial Long Window
      5. 5.6.5 Q&A
    7. 5.7 Communication Fault Monitoring
      1. 5.7.1 CAN
      2. 5.7.2 LIN
    8. 5.8 LIMP
  9. 6Programming, Memory, and Control
    1. 6.1 SPI
    2. 6.2 EEPROM
    3. 6.3 Interrupts
    4. 6.4 Control
  10. 7Miscellaneous Features
    1. 7.1 Local Wake Ups
    2. 7.2 CAN Bus Wake Up (BWRR)
    3. 7.3 Partial Networking
    4. 7.4 GFO, nRST, and SW
  11. 8Summary
  12. 9References

6.1 SPI

The TCAN28XX line of devices includes a 4-wire SPI bus. The SBC is a peripheral device and expects the controller to control the communication flow between SBC and controller. The SDO, SDI, and SCLK pins represent the serial data out, serial data in, and serial clock data for the SBC; while the nCS pin is the active low chip select line. The device defaults to SPI mode 0 and expects one-byte transactions without a CRC. The device does support SPI modes 1, 2, and 3 as well as two-byte transaction mode and one-byte transaction mode with CRC enabled. The maximum SPI speed is 4MHz for one-byte mode without CRC and 2MHz otherwise. Configuration, watchdog triggers, and saving configurations are all done through the SPI bus.