SLLA651 April   2025 TCAN2845-Q1 , TCAN2847-Q1 , TCAN2855-Q1 , TCAN2857-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Device States
    1. 2.1 Init Mode
    2. 2.2 Restart Mode
    3. 2.3 Standby Mode
    4. 2.4 Normal Mode
    5. 2.5 Sleep Mode
    6. 2.6 Fail-Safe Mode
  6. 3Power Electronics
    1. 3.1 VSUP
    2. 3.2 VHSS
    3. 3.3 VCAN
    4. 3.4 VCC1
    5. 3.5 VCC2
    6. 3.6 VEXMON, VEXCTRL, and VEXCC
    7. 3.7 HSSx
  7. 4Communication Capabilities
    1. 4.1 CAN-FD and Classical CAN
    2. 4.2 CAN-SIC
    3. 4.3 LIN
  8. 5Protection Features
    1. 5.1 Undervoltage (UV) Monitors
      1. 5.1.1 VSUP
      2. 5.1.2 VHSS
      3. 5.1.3 VCAN
      4. 5.1.4 VEXCC
      5. 5.1.5 VCC1
      6. 5.1.6 VCC2
    2. 5.2 Overvoltage (OV) Monitors
      1. 5.2.1 HSSx
      2. 5.2.2 VCC1
      3. 5.2.3 VCC2
      4. 5.2.4 VEXCC
    3. 5.3 Short Circuit (SC) Monitors
      1. 5.3.1 VCC1
      2. 5.3.2 VCC2
      3. 5.3.3 VEXCC
    4. 5.4 Electrical Faults and Impact on SBC Mode
    5. 5.5 Temperature Sensors
    6. 5.6 Watchdog
      1. 5.6.1 Watchdog Error Counter
      2. 5.6.2 Timeout
      3. 5.6.3 Window
      4. 5.6.4 Initial Long Window
      5. 5.6.5 Q&A
    7. 5.7 Communication Fault Monitoring
      1. 5.7.1 CAN
      2. 5.7.2 LIN
    8. 5.8 LIMP
  9. 6Programming, Memory, and Control
    1. 6.1 SPI
    2. 6.2 EEPROM
    3. 6.3 Interrupts
    4. 6.4 Control
  10. 7Miscellaneous Features
    1. 7.1 Local Wake Ups
    2. 7.2 CAN Bus Wake Up (BWRR)
    3. 7.3 Partial Networking
    4. 7.4 GFO, nRST, and SW
  11. 8Summary
  12. 9References

6.3 Interrupts

There are eight interrupt registers and one global interrupt register contained within the TCAN28XX line of devices. The global interrupt vector uses each bit as a logical OR’d output of a different interrupt register with the following structure.

Table 6-2 Global Interrupt Vector
Bit Position Data Comment
7 INT_7 Logical OR’d output of INT_7
6 INT_1 Logical OR’d output of INT_1
5 INT_2 Logical OR’d output of INT_2
4 INT_3 Logical OR’d output of INT_3
3 INT_CANBUS Logical OR’d output of INT_CANBUS
2 INT_4 Logical OR’d output of INT_4
1 INT_5 Logical OR’d output of INT_5
0 INT_6 Logical OR’d output of INT_6

Any issue that is flagged in one of interrupt registers can also show an interrupt in the global interrupt vector. Every SPI transaction that is performed on the device, regardless of SPI setup, can have the first byte out of the SDO pin as the global interrupt vector – so if an interrupt has been generated, this can show up here. If VCC1 is active, the interrupt generation can result in the nINT pin being pulled low. A full overview of interrupts can be seen in the following table.

Table 6-3 Device Interrupts
Register Address Bit Position Data Comment
INT_1 51h 7 WD Watchdog Error
INT_1 51h 6 CANINT1 CAN Bus Wake Up
INT_1 51h 5 LWU Local Wake Up
INT_1 51h 4 WKERR SWE Timer has Expired, SBC in sleep
INT_1 51h 3 FRAME_OVF_1 Frame Error Counter Overflow
INT_1 51h 2 CANSLNT_1 CAN bus silent for tSILENCE
INT_1 51h 1 SWPIN SW pin used to wake device
INT_1 51h 0 CANDOM_1 CAN Bus Stuck Dominant
INT_2 52h 7 SMS Sleep Mode Status: flagged when error causes device to go to sleep
INT_2 52h 6 PWRON Device Power is on
INT_2 52h 5 OVCC1 OV Event on VCC1
INT_2 52h 4 UVSUP5 VSUP UV event for 5V
INT_2 52h 3 UVSUP3 VSUP UV event for 3.3V
INT_2 52h 2 UVCC1 UV Event on VCC1
INT_2 52h 1 TSD_VCC1_VEXCC Thermal Shutdown due to VCC1 or VEXCC
INT_2 52h 0 SME Sleep Mode Exit – when SBC goes to restart mode or Fail-Safe from sleep with VCC1 on and fault occurs on VCC1
INT_3 53h 7 SPIERR Sets when SPI status bit is set
INT_3 53h 6 SWERR (SW_EN and (about SWCFG)) | FRAME_OVF
INT_3 53h 5 FSM Entered Fail-Safe Mode
INT_3 53h 4 CRCERR SPI CRC Error Detected
INT_3 53h 3 VCC1SC Short Circuit Event on VCC1
INT_3 53h 2 RSTR_CNT Restart Counter Exceeded Threshold
INT_3 53h 1 TSD_CAN_LIN Thermal Shutdown due to VCC2, CAN, or LIN
INT_3 53h 0 CRC_EEPROM EEPROM CRC Error
INT_CANBUS 54h 7 UVCAN UV Event on VCAN
INT_CANBUS 54h 6 RESERVED N/A
INT_CANBUS 54h 5 CANHCANL CANH and CANL shorted
INT_CANBUS 54h 4 CANHBAT CANH shorted to battery
INT_CANBUS 54h 3 CANLGND CANL shorted to GND
INT_CANBUS 54h 2 CANBUSOPEN CAN Bus Opened
INT_CANBUS 54h 1 CANBUSGND CANH shorted to GND or both CANH and CANL shorted to GND
INT_CANBUS 54h 0 CANBUSBAT CANL shorted to VBAT or both CANH and CANL shorted to VBAT
INT_7 55h 7 HSSOC1 HSS1 overcurrent
INT_7 55h 6 HSSOL1 HSS1 Open Load
INT_7 55h 5 HSSOC2 HSS2 overcurrent
INT_7 55h 4 HSSOL2 HSS2 Open Load
INT_7 55h 3 HSSOC3 HSS3 overcurrent
INT_7 55h 2 HSSOL3 HSS3 Open Load
INT_7 55h 1 HSSOC4 HSS4 overcurrent
INT_7 55h 0 HSSOL4 HSS4 Open Load
INT_4 5Ah 7 LIN1_WUP LIN 1 Bus Wake
INT_4 5Ah 6 LIN1_DTO LIN 1 Dominant Time Out
INT_4 5Ah 5 RSVD N/A
INT_4 5Ah 4 CYC_WUP Cyclic Wake-up via Timer
INT_4 5Ah 3 MODE_ERR Illegal Transceiver state for mode change request
INT_4 5Ah 2 OVHSS OV Event on VHSS
INT_4 5Ah 1 EEPROM_CRC_INT EEPROM saved configuration CRC error
INT_4 5Ah 0 UVHSS UV Event on VHSS
INT_6 5Ch 7 TSDW Thermal Shutdown Warning
INT_6 5Ch 6 UVCC1PW VCC1 UV Prewarning
INT_6 5Ch 5 UVEXCC UV Event on VEXCC
INT_6 5Ch 4 OVEXCC OV Event on VEXCC
INT_6 5Ch 3 VEXCCSC SC Event on VEXCC
INT_6 5Ch 2 UVCC2 UV Event on VCC2
INT_6 5Ch 1 OVCC2 OV Event on VCC2
INT_6 5Ch 0 VCC2SC SC Event on VCC2

Each interrupt vector has a companion mask register that allows an end user to disable interrupts that the user does not want to monitor for. Interrupt vectors can be cleared by writing 0xFF to an interrupt register that the end user wants to clear.