SLLSFZ8 November   2025 MCF8329HS-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  Low-Side Current Sense Amplifier
      5. 7.3.5  Device Interface Modes
        1. 7.3.5.1 Interface - Control and Monitoring
        2. 7.3.5.2 I2C Interface
      6. 7.3.6  Motor Control Input Options
        1. 7.3.6.1 Analog-Mode Motor Control
        2. 7.3.6.2 PWM-Mode Motor Control
        3. 7.3.6.3 Frequency-Mode Motor Control
        4. 7.3.6.4 I2C based Motor Control
        5. 7.3.6.5 Input Control Signal Profiles
          1. 7.3.6.5.1 Linear Control Profiles
          2. 7.3.6.5.2 Staircase Control Profiles
          3. 7.3.6.5.3 Forward-Reverse Profiles
          4. 7.3.6.5.4 Multi-Reference Mode Operation
          5. 7.3.6.5.5 Input Reference Transfer Function without Profiler
      7. 7.3.7  Bootstrap Capacitor Initial Charging
      8. 7.3.8  Starting the Motor Under Different Initial Conditions
        1. 7.3.8.1 Case 1 – Motor is Stationary
        2. 7.3.8.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.8.3 Case 3 – Motor is Spinning in the Reverse Direction
      9. 7.3.9  Motor Start Sequence (MSS)
        1. 7.3.9.1 Initial Speed Detect (ISD)
        2. 7.3.9.2 Motor Resynchronization
        3. 7.3.9.3 Reverse Drive
          1. 7.3.9.3.1 Reverse Drive Tuning
        4. 7.3.9.4 Motor Start-up
          1. 7.3.9.4.1 Align
          2. 7.3.9.4.2 Double Align
          3. 7.3.9.4.3 Initial Position Detection (IPD)
            1. 7.3.9.4.3.1 IPD Operation
            2. 7.3.9.4.3.2 IPD Release
            3. 7.3.9.4.3.3 IPD Advance Angle
          4. 7.3.9.4.4 Slow First Cycle Startup
          5. 7.3.9.4.5 Open Loop
          6. 7.3.9.4.6 Transition from Open to Closed Loop
      10. 7.3.10 Closed Loop Operation
        1. 7.3.10.1 Closed loop accelerate
        2. 7.3.10.2 Speed PI Control
        3. 7.3.10.3 Current PI Control
        4. 7.3.10.4 Overmodulation
        5. 7.3.10.5 Power Loop
        6. 7.3.10.6 Modulation Index Control
        7. 7.3.10.7 Motor Speed Limit
        8. 7.3.10.8 Input DC Power Limit
      11. 7.3.11 Maximum Torque Per Ampere (MTPA) Control
      12. 7.3.12 Flux Weakening Control
      13. 7.3.13 Motor Parameters
        1. 7.3.13.1 Motor Resistance
        2. 7.3.13.2 Motor Inductance
        3. 7.3.13.3 Motor Back-EMF constant
      14. 7.3.14 Motor Parameter Extraction Tool (MPET)
      15. 7.3.15 Single Hall Sensor Operation
      16. 7.3.16 Anti-Voltage Surge (AVS)
      17. 7.3.17 Active Braking
      18. 7.3.18 Output PWM Switching Frequency
      19. 7.3.19 Dead Time Compensation
      20. 7.3.20 Voltage Sense Scaling
      21. 7.3.21 Motor Stop Options
        1. 7.3.21.1 Coast (Hi-Z) Mode
        2. 7.3.21.2 Recirculation Mode
        3. 7.3.21.3 Low-Side Braking
        4. 7.3.21.4 Active Spin-Down
      22. 7.3.22 FG Configuration
        1. 7.3.22.1 FG Output Frequency
        2. 7.3.22.2 FG in Open-Loop
        3. 7.3.22.3 FG During Motor Stop
        4. 7.3.22.4 FG Behavior During Fault
      23. 7.3.23 Protections
        1. 7.3.23.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.23.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.23.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.23.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.23.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.23.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.23.7  Thermal Shutdown (OTSD)
        8. 7.3.23.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.23.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xb or 010b)
          2. 7.3.23.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 011b or 10xb)
          3. 7.3.23.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 110b)
          4. 7.3.23.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE = 111b)
        9. 7.3.23.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.23.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xb or 010b)
          2. 7.3.23.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 011b or 10xb)
          3. 7.3.23.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 110b)
          4. 7.3.23.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 111b)
        10. 7.3.23.10 Motor Lock (MTR_LCK)
          1. 7.3.23.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xb or 010b)
          2. 7.3.23.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE = 011b or 10xb)
          3. 7.3.23.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 110b)
          4. 7.3.23.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 111b)
        11. 7.3.23.11 Motor Lock Detection
          1. 7.3.23.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.23.11.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.23.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.23.12 MPET Faults
        13. 7.3.23.13 IPD Faults
        14. 7.3.23.14 Dry Run Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 Oscillator Source
      3. 7.5.3 External Watchdog with MCU Reset
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
        3. 7.6.1.3 EEPROM Security
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
  9. 8 EEPROM (Non-Volatile) Register Map
    1. 8.1 Algorithm_Configuration Registers
    2. 8.2 Fault_Configuration Registers
    3. 8.3 Hardware_Configuration Registers
    4. 8.4 Internal_Algorithm_Configuration Registers
  10. 9 RAM (Volatile) Register Map
    1. 9.1 Fault_Status Registers
    2. 9.2 System_Status Registers
    3. 9.3 Algorithm_Control Registers
    4. 9.4 Device_Control Registers
    5. 9.5 Algorithm_Variables Registers
  11. 10Typical Applications
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3.      Gate Drive Current
      4.      Gate Resistor Selection
      5.      System Considerations in High Power Designs
      6.      Capacitor Voltage Ratings
      7.      External Power Stage Components
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Bulk Capacitance
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
      3. 10.4.3 Thermal Considerations
        1. 10.4.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

MCF8329HS-Q1 MCF8329HS-Q132-Pin WQFN With Exposed Thermal PadTop View Figure 5-1 MCF8329HS-Q132-Pin WQFN With Exposed Thermal PadTop View
Table 5-1 Pin Functions
PIN 32-pin package TYPE(1) DESCRIPTION
NAME MCF8329HS-Q1
AGND 23 GND Device analog ground
AVDD 24 PWR 3.3 or 5V regulator output. Connect a X7R, 1μF or 2.2μF, 10V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 50mA for external circuits. AVDD capacitor should have an effective capacitance between 0.5μF and 2.8μF after operating voltage (AVDD) and temperature derating.
BSTA 7 O Bootstrap output pin. Connect a X7R, 1µF, 25V ceramic capacitor between BSTA and SHA.
BSTB 11 O Bootstrap output pin. Connect a X7R, 1µF, 25V ceramic capacitor between BSTB and SHB.
BSTC 15 O Bootstrap output pin. Connect a X7R, 1µF, 25V ceramic capacitor between BSTC and SHC.
CPH 5 PWR Charge pump switching node. Connect a X7R, PVDD-rated ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin.
CPL 4 PWR
DGND 1 GND Device digital ground
DRVOFF 22 I Independent driver shutdown path. Pulling DRVOFF high turns off all external MOSFETs by putting the gate drivers into the pull-down state. This signal bypasses and overrides the digital and control core.
DVDD 32 PWR 1.5V internal regulator output. Connect a X7R, 1μF or 2.2µF,10V ceramic capacitor between the DVDD and DGND pins. DVDD capacitor should have an effective capacitance between 0.5μF and 2.8μF after operating voltage (DVDD) and temperature derating.
EXT_WD 29 I Watchdog input for external MCU monitoring
FG 26 O Motor speed indicator: open-drain output that requires a pull-up resistor to 1.8 to 5V. An optional internal pull-up resistor to AVDD can be enabled by setting PULLUP_ENABLE to 1b; no external pull-up resistor should be used when internal pull-up resistor is enabled.
GHA 9 O High-side gate driver output. Connect to the gate of the high-side power MOSFET
GHB 13 O High-side gate driver output. Connect to the gate of the high-side power MOSFET
GHC 17 O High-side gate driver output. Connect to the gate of the high-side power MOSFET
GLA 10 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET
GLB 14 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET
GLC 18 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET
GND 2 GND Device power ground
GVDD 6 PWR Gate driver power supply output. Connect a X7R, 30V rated ceramic ≥ 10µF local capacitance between the GVDD and GND pins. TI recommends a capacitor value of >10x CBSTx and voltage rating at least twice the normal operating voltage of the pin.
HALL_IN/nMCU_RST 30 I/O Multi-purpose pin. Single (3.3V or 5V) digital hall latch (optional) input for redundancy in motor lock detection or active-low (with internal pull-up to AVDD) reset signal to external MCU in case of watchdog timeout fault.
LSS 19 PWR Low side source pin, connect all sources of the external low-side MOSFETs here. This pin is the sink path for the low-side gate driver, and serves as an input to monitor the low-side MOSFET VDS voltage and VSEN_OCP voltage.
nFAULT 31 O Fault indicator. Pulled logic-low during fault condition; open-drain output that requires a pull-up resistor to 1.8V to 5V. An optional internal pull-up resistor to AVDD is enabled by setting PULLUP_ENABLE to 1b; no external pull-up resistor should be used when internal pull-up resistor is enabled
PVDD 3 PWR Gate driver power supply input. Connect to the bridge power supply. Connect a X7R, 0.1µF, >2x PVDD-rated ceramic and >10µF local capacitance between the PVDD and GND pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin.
SCL 28 I I2C clock input
SDA 27 I/O I2C data line
SHA 8 I/O High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink.
SHB 12 I/O High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink.
SHC 16 I/O High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink.
SN 21 I Current sense amplifier input. Connect to the low-side of the current shunt resistor.
SP 20 I Low-side current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPEED/WAKE 25 I Multifunction input.
Device sleep/wake input.
Device speed input; supports analog, PWM or frequency based reference (speed or current or power or voltage) input.
Thermal pad - PWR Must be connected to ground
(1) I = input, O = output, GND = ground pin, PWR = power, NC = no connect