SLLSFZ8 Data sheet | 德州仪器 TI.com.cn

SLLSFZ8 November 2025 MCF8329HS-Q1

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RRY|32
- MPQF713A

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RRY|32
- QFND763

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sllsfz8_oa

8.3 Hardware_Configuration Registers

Table 8-21 lists the memory-mapped registers for the Hardware_Configuration registers. All register offset addresses not listed in Table 8-21 should be considered as reserved locations and the register contents should not be modified.

Table 8-21 HARDWARE_CONFIGURATION Registers

Offset	Acronym	Register Name	Section
A4h	PIN_CONFIG	Hardware Pin Configuration	Section 8.3.1
A6h	DEVICE_CONFIG1	Device configuration1	Section 8.3.2
A8h	DEVICE_CONFIG2	Device configuration2	Section 8.3.3
AAh	PERI_CONFIG1	Peripheral Configuration1	Section 8.3.4
ACh	GD_CONFIG1	Gate Driver Configuration1	Section 8.3.5
AEh	GD_CONFIG2	Gate Driver Configuration2	Section 8.3.6

Complex bit access types are encoded to fit into small table cells. Table 8-22 shows the codes that are used for access types in this section.

Table 8-22 Hardware_Configuration Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.3.1 PIN_CONFIG Register (Offset = A4h) [Reset = 00000000h]

PIN_CONFIG is shown in Figure 8-17 and described in Table 8-23.

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Figure 8-17 PIN_CONFIG Register

31	30	29	28	27	26	25	24
PARITY	FLUX_WEAKENING_CURRENT_RATIO			LEAD_ANGLE
R-0h	R/W-0h			R/W-0h

23	22	21	20	19	18	17	16
LEAD_ANGLE		MAX_POWER
R/W-0h		R/W-0h

15	14	13	12	11	10	9	8
MAX_POWER					FG_IDLE_CONFIG		FG_FAULT_CONFIG
R/W-0h					R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
FG_FAULT_CONFIG	HALL_SNS_STARTUP_EN	HALL_EN	nMCU_RST	BRAKE_INPUT		SPEED_MODE
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h

Table 8-23 PIN_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R	0h	Parity bit
30-28	FLUX_WEAKENING_CURRENT_RATIO	R/W	0h	Maximum flux weakening current reference (% of ILIMIT) 0h = Circular current limit 1h = 80% 2h = 70% 3h = 60% 4h = 50% 5h = 40% 6h = 30% 7h = 20%
27-22	LEAD_ANGLE	R/W	0h	Lead angle. In Modulation index control, positive value indicates the applied voltage is leading the BEMF, negative value indicates applied voltage is lagging the BEMF. In other modes, positive means positive id reference, negative means negative id reference Lead angle (degrees) 0- 31 = 1.5 × LEAD_ANGLE 32 - 63 = 1.5 × (LEAD_ANGLE -64)
21-11	MAX_POWER	R/W	0h	Maximum power (Watts) 0- 1023 = 1 × MAX_POWER 1024 - 2047 = 2 × (MAX_POWER -1024) + 1024
10-9	FG_IDLE_CONFIG	R/W	0h	FG configuration during motor idle state 0h = FG is set by last driven state 1h = FG is Hi-Z (Externally pulled up) 2h = FG is pulled to Low 3h = FG is Hi-Z (Externally pulled up)
8-7	FG_FAULT_CONFIG	R/W	0h	FG configuration during fault state. BEMF threshold defined by FG_BEMF_THR if FG_CONFIG 1 0h = FG is pulled to Low 1h = FG is Hi-Z (Externally pulled up) 2h = FG reports fault type as a unique duty cycle at 1 Hz 3h = FG active till BEMF drops below BEMF threshold defined by FG_BEMF_THR if FG_CONFIG is 1
6	HALL_SNS_STARTUP_EN	R/W	0h	Hall sensor-based motor startup enable 0h = Disable 1h = Enable
5	HALL_EN	R/W	0h	Hall sensor input enable 0h = Disable 1h = Enable
4	nMCU_RST	R/W	0h	External MCU reset signal duration during watchdog fault 0h = 1 ms 1h = 5 ms
3-2	BRAKE_INPUT	R/W	0h	Brake pin mode 0h = Not Applicable 1h = Override pin and brake according to BRAKE_PIN_MODE 2h = Override pin and do not brake / align 3h = Not Applicable
1-0	SPEED_MODE	R/W	0h	Configure reference command mode from speed/wake pin 0h = Analog mode 1h = Controlled by duty cycle of SPEED input pin 2h = Register override mode 3h = Controlled by frequency of SPEED input pin

8.3.2 DEVICE_CONFIG1 Register (Offset = A6h) [Reset = 000XXXX0h]

DEVICE_CONFIG1 is shown in Figure 8-18 and described in Table 8-24.

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Figure 8-18 DEVICE_CONFIG1 Register

31	30	29	28	27	26	25	24
PARITY	MTPA_EN	RESERVED		RESERVED	I2C_TARGET_ADDR
R-0h	R/W-0h	R-0h		R-0h	R/W-0h

23	22	21	20	19	18	17	16
I2C_TARGET_ADDR				EEPROM_LOCK_KEY
R/W-0h				R/W-XXXh

15	14	13	12	11	10	9	8
EEPROM_LOCK_KEY
R/W-XXXh

7	6	5	4	3	2	1	0
EEPROM_LOCK_KEY			SLEW_RATE_I2C_PINS		PULLUP_ENABLE	BUS_VOLT
R/W-XXXh			R/W-0h		R/W-0h	R/W-0h

Table 8-24 DEVICE_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R	0h	Parity bit
30	MTPA_EN	R/W	0h	Maximum Torque Per Ampere (MTPA) operation enable 0h = Disable 1h = Enable
29-28	RESERVED	R	0h	Reserved
27	RESERVED	R	0h	Reserved
26-20	I2C_TARGET_ADDR	R/W	0h	I2C target address
19-5	EEPROM_LOCK_KEY	R/W	0h	EEPROM lock access key. This value when read will always show 0
4-3	SLEW_RATE_I2C_PINS	R/W	0h	I2C pins slew rate configuration 0h = 4.8 mA 1h = 3.9 mA 2h = 1.86 mA 3h = 30.8 mA
2	PULLUP_ENABLE	R/W	0h	Internal pull-up to AVDD enable for nFAULT and FG pins 0h = Disable 1h = Enable
1-0	BUS_VOLT	R/W	0h	Maximum PVDD voltage configuration. Voltage gain = 20 V/V, BUS_VOLT = 60 Voltage gain = 10 V/V, BUS_VOLT = 30 Voltage gain = 5 V/V, BUS_VOLT = 15 0h = 15 V 1h = 30 V 2h = 60 V 3h = Not defined

8.3.3 DEVICE_CONFIG2 Register (Offset = A8h) [Reset = 00000000h]

DEVICE_CONFIG2 is shown in Figure 8-19 and described in Table 8-25.

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Figure 8-19 DEVICE_CONFIG2 Register

31	30	29	28	27	26	25	24
PARITY	INPUT_MAXIMUM_FREQ
R-0h	R/W-0h

23	22	21	20	19	18	17	16
INPUT_MAXIMUM_FREQ
R/W-0h

15	14	13	12	11	10	9	8
SLEEP_ENTRY_TIME		LIMP_HOME_EN	DYNAMIC_VOLTAGE_GAIN_EN	DEV_MODE	PWM_DITHER_DEPTH		RESERVED
R/W-0h		R/W-0h	R/W-0h	R/W-0h	R/W-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED			EXT_WD_EN	EXT_WD_CONFIG		EXT_WD_INPUT_MODE	EXT_WD_FAULT_MODE
R-0h			R/W-0h	R/W-0h		R/W-0h	R/W-0h

Table 8-25 DEVICE_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R	0h	Parity bit
30-16	INPUT_MAXIMUM_FREQ	R/W	0h	Speed pin input frequency configuration for frequency control mode that corresponds to 100% duty cycle Input duty cycle = Input frequency / INPUT_MAXIMUM_FREQ
15-14	SLEEP_ENTRY_TIME	R/W	0h	Sleep command detection time. (Refer Table: Conditions to Enter or Exit Sleep Modes) 0h = 50 µs 1h = 200 µs 2h = 20 ms 3h = 200 ms
13	LIMP_HOME_EN	R/W	0h	Limp home mode enable 0h = Disable 1h = Enable
12	DYNAMIC_VOLTAGE_GAIN_EN	R/W	0h	Dynamic voltage gain adjustment enable 0h = Disable 1h = Enable
11	DEV_MODE	R/W	0h	Device mode select 0h = Standby mode 1h = Sleep mode
10-9	PWM_DITHER_DEPTH	R/W	0h	PWM dither depth 0h = PWM dither disabled 1h = 5% 2h = 7.5% 3h = 10%
8	RESERVED	R	0h	Reserved
7-5	RESERVED	R	0h	Reserved
4	EXT_WD_EN	R/W	0h	External watchdog enable 0h = Disable 1h = Enable
3-2	EXT_WD_CONFIG	R/W	0h	Time between watchdog tickles (GPIO/I2C) 0h = 100 ms/1 s 1h = 200 ms/2 s 2h = 500 ms/5 s 3h = 1000 ms/10 s
1	EXT_WD_INPUT_MODE	R/W	0h	External watchdog input source 0h = Watchdog tickle over I2C 1h = Watchdog tickle over GPIO
0	EXT_WD_FAULT_MODE	R/W	0h	External watchdog fault mode 0h = External watchdog fault causes report only but no action is taken; nFAULT is active 1h = External watchdog fault causes latched fault; nFAULT is active; Gate driver is tristated

8.3.4 PERI_CONFIG1 Register (Offset = AAh) [Reset = 40000000h]

PERI_CONFIG1 is shown in Figure 8-20 and described in Table 8-26.

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Figure 8-20 PERI_CONFIG1 Register

31	30	29	28	27	26	25	24
PARITY	SPREAD_SPECTRUM_MODULATION_DIS	DIG_DEAD_TIME				CLOCK_FREQUENCY
R-0h	R/W-1h	R/W-0h				R/W-0h

23	22	21	20	19	18	17	16
VDC_FILTER		BUS_POWER_LIMIT_ENABLE	DIR_INPUT		DIR_CHANGE_MODE	SPEED_LIMIT_ENABLE	RESERVED
R/W-0h		R/W-0h	R/W-0h		R/W-0h	R/W-0h	R-0h

15	14	13	12	11	10	9	8
ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY			PWM_DITHER_MODE	PWM_DITHER_STEP		SPEED_RANGE_SEL	NO_MTR_FLT_CLOSEDLOOP_DIS
R/W-0h			R/W-0h	R/W-0h		R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
FLUX_WEAKENING_REFERENCE		CTRL_MODE		SALIENCY_PERCENTAGE
R/W-0h		R/W-0h		R/W-0h

Table 8-26 PERI_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R	0h	Parity bit
30	SPREAD_SPECTRUM_MODULATION_DIS	R/W	1h	Spread Spectrum Modulation (SSM) disable 0h = SSM is enabled 1h = SSM is disabled
29-26	DIG_DEAD_TIME	R/W	0h	PWM dead time configuration 0h = Not Applicable 1h = Not Applicable 2h = 100 ns 3h = 150 ns 4h = 200 ns 5h = 250 ns 6h = 300 ns 7h = 350 ns 8h = 400 ns 9h = 450 ns Ah = 500 ns Bh = 600 ns Ch = 700 ns Dh = 800 ns Eh = 900 ns Fh = 1000 ns
25-24	CLOCK_FREQUENCY	R/W	0h	System clock frequency configuration 0h = High 1h = Medium 2h = Low 3h = Reserved
23-22	VDC_FILTER	R/W	0h	PVDD voltage filter coefficient 0h = Disable 1h = Enable with default filter cut-off frequency 2h = Enable with filter cut-off frequency 100 Hz 3h = Enable with filter cut-off frequency 1000 Hz
21	BUS_POWER_LIMIT_ENABLE	R/W	0h	Bus power limit enable (Limits input DC bus power to MAX_POWER except if CTRL_MODE = 1h) 0h = Disable 1h = Enable
20-19	DIR_INPUT	R/W	0h	Direction (DIR) pin override 0h = Not Applicable 1h = Override DIR pin with clockwise rotation OUTA-OUTB-OUTC 2h = Override DIR pin with counter clockwise rotation OUTA-OUTC-OUTB 3h = Not Applicable
18	DIR_CHANGE_MODE	R/W	0h	Response to direction change command (Refer Figure: Motor Starting-up Flow) 0h = Follow motor stop options and ISD routine on detecting DIR change 1h = Change the direction through reverse drive while continuously driving the motor
17	SPEED_LIMIT_ENABLE	R/W	0h	Motor speed limit enable (Limits motor speed to MAX_SPEED except if CTRL_MODE = 0h) 0h = Disable 1h = Enable
16	RESERVED	R	0h	Reserved
15-13	ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY	R/W	0h	Difference between final speed and present speed below which active braking will be applied (% of MAX_SPEED) 0h = 20% 1h = 30% 2h = 40% 3h = 50% 4h = 60% 5h = 70% 6h = 80% 7h = 90%
12	PWM_DITHER_MODE	R/W	0h	PWM dither mode 0h = Triangular mode 1h = Random mode
11-10	PWM_DITHER_STEP	R/W	0h	PWM dither step 0h = 1 1h = 2 2h = 5 3h = 10
9	SPEED_RANGE_SEL	R/W	0h	Frequency range selection for PWM duty mode reference input (SPEED_MODE = 1h) 0h = 325 Hz to 100 kHz speed PWM input 1h = 10 Hz to 325 Hz speed PWM input
8	NO_MTR_FLT_CLOSEDLOOP_DIS	R/W	0h	No motor fault detection enable in closed-loop 0h = Enable No motor fault in closed loop if LOCK2_EN is set to 0x1 1h = Disable No Motor fault in closed loop
7-6	FLUX_WEAKENING_REFERENCE	R/W	0h	Modulation index reference to be tracked in flux weakening mode 0h = 70% 1h = 80% 2h = 90% 3h = 95%
5-4	CTRL_MODE	R/W	0h	Control mode 0h = Speed control 1h = Power control 2h = Current control 3h = Modulation index control
3-0	SALIENCY_PERCENTAGE	R/W	0h	Motor saliency in percentage calculated as ((Lq-Ld) × 100)/(4 × (Lq+Ld)) Example: Lq = 2mH and Ld = 1mH then SALIENCY_PERCENTAGE = 100/12 = 8.33 (Configure 8)

8.3.5 GD_CONFIG1 Register (Offset = ACh) [Reset = 00000000h]

GD_CONFIG1 is shown in Figure 8-21 and described in Table 8-27.

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Figure 8-21 GD_CONFIG1 Register

31	30	29	28	27	26	25	24
PARITY	RESERVED					BST_CHRG_TIME
R-0h	R-0h					R/W-0h

23	22	21	20	19	18	17	16
SNS_FLT_MODE	VDS_FLT_MODE	BST_UV_MODE	GVDD_UV_MODE	AVDD_VOL_SEL	RESERVED	RESERVED	DIS_BST_FLT
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R-0h	R-0h	R/W-0h

15	14	13	12	11	10	9	8
OTS_AUTO_RECOVERY	RESERVED					DIS_SNS_FLT	DIS_VDS_FLT
R/W-0h	R-0h					R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED	SEL_VDS_LVL				RESERVED	CSA_GAIN
R-0h	R/W-0h				R-0h	R/W-0h

Table 8-27 GD_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R	0h	Parity bit
30-26	RESERVED	R	0h	Reserved
25-24	BST_CHRG_TIME	R/W	0h	Bootstrap capacitor charging time 0h = 0 ms 1h = 3 ms 2h = 6 ms 3h = 12 ms
23	SNS_FLT_MODE	R/W	0h	Current sense overcurrent fault mode 0h = Current sense overcurrent fault causes latched fault; nFAULT active; Gate driver is tristated 1h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active
22	VDS_FLT_MODE	R/W	0h	VDS overcurrent fault response mode 0h = VDS overcurrent fault causes latched fault; nFAULT active; Gate driver is tristated 1h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active
21	BST_UV_MODE	R/W	0h	Bootstrap undervoltage fault mode 0h = Bootstrap undervoltage fault causes latched fault; nFAULT active; Gate driver is tristated 1h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active
20	GVDD_UV_MODE	R/W	0h	GVDD undervoltage fault mode 0h = GVDD undervoltage fault causes latched fault; nFAULT active; Gate driver is tristated 1h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active
19	AVDD_VOL_SEL	R/W	0h	AVDD voltage level selection 0h = 3.3 V 1h = 5 V
18	RESERVED	R	0h	Reserved
17	RESERVED	R	0h	Reserved
16	DIS_BST_FLT	R/W	0h	Bootstrap fault detection disable 0h = Enable BST fault 1h = Disable BST fault
15	OTS_AUTO_RECOVERY	R/W	0h	Over-temperature shutdown (OTS) auto recovery enable 0h = OTS fault causes latched fault; nFAULT active; Gate driver is tristated 1h = OTS fault clears automatically if (TJ < TOTSD – THYS);Gate driver is tristated; nFAULT active
14-10	RESERVED	R	0h	Reserved
9	DIS_SNS_FLT	R/W	0h	Current sense fault detection disable 0h = Enable SNS OCP fault 1h = Disable SNS OCP fault
8	DIS_VDS_FLT	R/W	0h	VDS fault detection disable 0h = Enable VDS fault 1h = Disable VDS fault
7	RESERVED	R	0h	Reserved
6-3	SEL_VDS_LVL	R/W	0h	VDS overcurrent protection threshold 0h = 0.06 V 1h = 0.12 V 2h = 0.18 V 3h = 0.24 V 4h = 0.3 V 5h = 0.36 V 6h = 0.42 V 7h = 0.48 V 8h = 0.6 V 9h = 0.8 V Ah = 1 V Bh = 1.2 V Ch = 1.4 V Dh = 1.6 V Eh = 1.8 V Fh = 2 V
2	RESERVED	R	0h	Reserved
1-0	CSA_GAIN	R/W	0h	Current Sense Amplifier (CSA) gain 0h = 5 V/V 1h = 10 V/V 2h = 20 V/V 3h = 40 V/V

8.3.6 GD_CONFIG2 Register (Offset = AEh) [Reset = 00000000h]

GD_CONFIG2 is shown in Figure 8-22 and described in Table 8-28.

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Figure 8-22 GD_CONFIG2 Register

31	30	29	28	27	26	25	24
PARITY	RESERVED
R-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED	BASE_CURRENT
R-0h	R/W-0h

7	6	5	4	3	2	1	0
BASE_CURRENT
R/W-0h

Table 8-28 GD_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R	0h	Parity bit
30-15	RESERVED	R	0h	Reserved
14-0	BASE_CURRENT	R/W	0h	Base current calculated based on gain settings Base current in Ampere = 1.5/(RSENSE × CSA_GAIN) BASE_CURRENT = Base current in Ampere × 32768/1200 Example: for 30A, enter 30 × 32768 / 1200 = 820