SLLSFZ8 November   2025 MCF8329HS-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  Low-Side Current Sense Amplifier
      5. 7.3.5  Device Interface Modes
        1. 7.3.5.1 Interface - Control and Monitoring
        2. 7.3.5.2 I2C Interface
      6. 7.3.6  Motor Control Input Options
        1. 7.3.6.1 Analog-Mode Motor Control
        2. 7.3.6.2 PWM-Mode Motor Control
        3. 7.3.6.3 Frequency-Mode Motor Control
        4. 7.3.6.4 I2C based Motor Control
        5. 7.3.6.5 Input Control Signal Profiles
          1. 7.3.6.5.1 Linear Control Profiles
          2. 7.3.6.5.2 Staircase Control Profiles
          3. 7.3.6.5.3 Forward-Reverse Profiles
          4. 7.3.6.5.4 Multi-Reference Mode Operation
          5. 7.3.6.5.5 Input Reference Transfer Function without Profiler
      7. 7.3.7  Bootstrap Capacitor Initial Charging
      8. 7.3.8  Starting the Motor Under Different Initial Conditions
        1. 7.3.8.1 Case 1 – Motor is Stationary
        2. 7.3.8.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.8.3 Case 3 – Motor is Spinning in the Reverse Direction
      9. 7.3.9  Motor Start Sequence (MSS)
        1. 7.3.9.1 Initial Speed Detect (ISD)
        2. 7.3.9.2 Motor Resynchronization
        3. 7.3.9.3 Reverse Drive
          1. 7.3.9.3.1 Reverse Drive Tuning
        4. 7.3.9.4 Motor Start-up
          1. 7.3.9.4.1 Align
          2. 7.3.9.4.2 Double Align
          3. 7.3.9.4.3 Initial Position Detection (IPD)
            1. 7.3.9.4.3.1 IPD Operation
            2. 7.3.9.4.3.2 IPD Release
            3. 7.3.9.4.3.3 IPD Advance Angle
          4. 7.3.9.4.4 Slow First Cycle Startup
          5. 7.3.9.4.5 Open Loop
          6. 7.3.9.4.6 Transition from Open to Closed Loop
      10. 7.3.10 Closed Loop Operation
        1. 7.3.10.1 Closed loop accelerate
        2. 7.3.10.2 Speed PI Control
        3. 7.3.10.3 Current PI Control
        4. 7.3.10.4 Overmodulation
        5. 7.3.10.5 Power Loop
        6. 7.3.10.6 Modulation Index Control
        7. 7.3.10.7 Motor Speed Limit
        8. 7.3.10.8 Input DC Power Limit
      11. 7.3.11 Maximum Torque Per Ampere (MTPA) Control
      12. 7.3.12 Flux Weakening Control
      13. 7.3.13 Motor Parameters
        1. 7.3.13.1 Motor Resistance
        2. 7.3.13.2 Motor Inductance
        3. 7.3.13.3 Motor Back-EMF constant
      14. 7.3.14 Motor Parameter Extraction Tool (MPET)
      15. 7.3.15 Single Hall Sensor Operation
      16. 7.3.16 Anti-Voltage Surge (AVS)
      17. 7.3.17 Active Braking
      18. 7.3.18 Output PWM Switching Frequency
      19. 7.3.19 Dead Time Compensation
      20. 7.3.20 Voltage Sense Scaling
      21. 7.3.21 Motor Stop Options
        1. 7.3.21.1 Coast (Hi-Z) Mode
        2. 7.3.21.2 Recirculation Mode
        3. 7.3.21.3 Low-Side Braking
        4. 7.3.21.4 Active Spin-Down
      22. 7.3.22 FG Configuration
        1. 7.3.22.1 FG Output Frequency
        2. 7.3.22.2 FG in Open-Loop
        3. 7.3.22.3 FG During Motor Stop
        4. 7.3.22.4 FG Behavior During Fault
      23. 7.3.23 Protections
        1. 7.3.23.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.23.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.23.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.23.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.23.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.23.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.23.7  Thermal Shutdown (OTSD)
        8. 7.3.23.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.23.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xb or 010b)
          2. 7.3.23.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 011b or 10xb)
          3. 7.3.23.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 110b)
          4. 7.3.23.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE = 111b)
        9. 7.3.23.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.23.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xb or 010b)
          2. 7.3.23.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 011b or 10xb)
          3. 7.3.23.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 110b)
          4. 7.3.23.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 111b)
        10. 7.3.23.10 Motor Lock (MTR_LCK)
          1. 7.3.23.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xb or 010b)
          2. 7.3.23.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE = 011b or 10xb)
          3. 7.3.23.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 110b)
          4. 7.3.23.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 111b)
        11. 7.3.23.11 Motor Lock Detection
          1. 7.3.23.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.23.11.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.23.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.23.12 MPET Faults
        13. 7.3.23.13 IPD Faults
        14. 7.3.23.14 Dry Run Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 Oscillator Source
      3. 7.5.3 External Watchdog with MCU Reset
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
        3. 7.6.1.3 EEPROM Security
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
  9. 8 EEPROM (Non-Volatile) Register Map
    1. 8.1 Algorithm_Configuration Registers
    2. 8.2 Fault_Configuration Registers
    3. 8.3 Hardware_Configuration Registers
    4. 8.4 Internal_Algorithm_Configuration Registers
  10. 9 RAM (Volatile) Register Map
    1. 9.1 Fault_Status Registers
    2. 9.2 System_Status Registers
    3. 9.3 Algorithm_Control Registers
    4. 9.4 Device_Control Registers
    5. 9.5 Algorithm_Variables Registers
  11. 10Typical Applications
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3.      Gate Drive Current
      4.      Gate Resistor Selection
      5.      System Considerations in High Power Designs
      6.      Capacitor Voltage Ratings
      7.      External Power Stage Components
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Bulk Capacitance
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
      3. 10.4.3 Thermal Considerations
        1. 10.4.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

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7.3.23 Protections

The MCF8329HS-Q1 is protected from a host of fault events including motor lock, PVDD undervoltage, AVDD undervoltage, GVDD undervoltage, bootstrap undervoltage, overtemperature and overcurrent events. Table 7-6 summarizes the response, recovery modes, gate driver status, reporting mechanism for different faults.

Note:
  1. Actionable and report only faults (latched or retry) are always reported on nFAULT pin (as logic low).
  2. Priority order for multi-fault scenarios is latched > slower retry time fault > faster retry time fault > report only fault. For example, if a latched and retry fault happen simultaneously, the device stays latched in fault mode until user issues clear fault command by writing 1b to CLR_FLT or through a power recycle. If two retry faults with different retry times happen simultaneously, the device retries only after the longer (slower) retry time lapses.
  3. Recovery refers only to state of gate driver after the fault condition is removed. Automatic indicates that the device automatically recovers (and gate driver outputs and hence external FETs are active) when retry time lapses after the fault condition is removed. Latched indicates that the device waits for clearing of fault condition (by writing 1b to CLR_FLT bit) or through a power recycle.
  4. The GVDD undervoltage, BST under voltage, VDS OCP, SENSE OCP faults can take up to 200ms after fault response (gate driver outputs pulled low to put the external FETs in Hi-Z) to be reported on nFAULT pin (as logic low).
  5. Latched faults can take up to 200ms after CLR_FLT command is issued (over I2C) to be cleared.
  6. CLR_FLT command (over I2C) will clear all the faults (and corresponding fault status bits) including latched, automatic recovery (retry) and report only faults.
  7. When device resumes normal operation after retry time (of an automatic recovery fault) lapses, fault status bits of all automatic recovery (retry) and report only faults set to 1b are cleared (reset to 0b) automatically.
Table 7-6 Fault Action and Response
FAULT CONDITION CONFIGURATION REPORT GATE DRIVER LOGIC RECOVERY
PVDD under-voltage
(PVDD_UV) 		VPVDD < VPVDD_UV — nFAULT Disabled Disabled Automatic:
VPVDD > VPVDD_UV
AVDD POR
(AVDD_POR)		 VAVDD < VAVDD_POR — nFAULT Disabled Disabled Automatic:
VAVDD > VAVDD_POR
GVDD under-voltage
(GVDD_UV)		 VGVDD < VGVDD_UV GVDD_UV_MODE = 0b nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low (1) Active Latched:
CLR_FLT
GVDD_UV_MODE = 1b nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low (1) Active Retry:
tLCK_RETRY
BSTx under-voltage
(BST_UV) 		VBSTx - VSHx < VBST_UV

DIS_BST_FLT = 0b

BST_UV_MODE = 0b

 nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low (1) Active Latched:
CLR_FLT

DIS_BST_FLT = 0b

BST_UV_MODE = 1b

 nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low (1) Active Retry:
tLCK_RETRY
VDS overcurrent
(VDS_OCP) 		VDS > VSEL_VDS_LVL

DIS_VDS_FLT = 0b

VDS_FLT_MODE = 0b

 nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low (1) Active Latched:
CLR_FLT

DIS_VDS_FLT = 0b

VDS_FLT_MODE = 1b

 nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low (1) Active Retry:
tLCK_RETRY
VSENSE overcurrent
(SEN_OCP)VSENSE overcurrent
(SEN_OCP)		 VSP > VSENSE_LVL

DIS_SNS_FLT = 0b

SNS_FLT_MODE = 0b

 nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low (1) Active Latched:
CLR_FLT

DIS_SNS_FLT = 0b

SNS_FLT_MODE = 1b

 nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low (1) Active Retry:
tLCK_RETRY
3 Motor Lock
(MTR_LCK )		 Motor lock: Abnormal Speed; No Motor Lock; Abnormal BEMF MTR_LCK_MODE = 000b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low (1)(MOSFETs in Hi-Z) Active Latched:
CLR_FLT
MTR_LCK_MODE = 001b or 010b nFAULT and CONTROLLER_FAULT_STATUS register Low side brake Active Latched:
CLR_FLT
MTR_LCK_MODE = 011b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low (1)(MOSFETs in Hi-Z) Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 100b or 101b nFAULT and CONTROLLER_FAULT_STATUS register Low side brake Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 110b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
MTR_LCK_MODE = 111b None Active Active No action
Hardware Lock-Detection Current Limit
(HW_LOCK_ILIMIT)
Phase Current > HW_LOCK_ILIMIT HW_LOCK_ILIMIT_MODE = 000b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low (1)(MOSFETs in Hi-Z) Active Latched:
CLR_FLT
HW_LOCK_ILIMIT_MODE = 001b or 010b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Latched:
CLR_FLT
HW_LOCK_ILIMIT_MODE = 011b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low (1)(MOSFETs in Hi-Z) Active Retry:
tLCK_RETRY
HW_LOCK_ILIMIT_MODE = 100b or 101b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Retry:
tLCK_RETRY
HW_LOCK_ILIMIT_MODE= 110b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
HW_LOCK_ILIMIT_MODE = 111b None Active Active No action
ADC based Lock-Detection Current Limit
(LOCK_ILIMIT)
Phase Current > LOCK_ILIMIT LOCK_ILIMIT_MODE = 000b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low (1)(MOSFETs in Hi-Z) Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 001b or 010b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 011b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low (1)(MOSFETs in Hi-Z) Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE = 100b or 101b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE= 110b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
LOCK_ILIMIT_MODE = 111b None Active Active No action
MPET Back-EMF Fault
(MPET_BEMF_FAULT)		 Motor Back EMF < STAT_DETECT_THR MPET_CMD = 1 or
MPET_KE = 1		 nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
Maximum VPVDD (over-voltage) fault VPVDD > MAX_VM_MOTOR, if MAX_VM_MOTOR ≠ 000b MAX_VM_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low (1)(MOSFETs in Hi-Z) Active Latched:
CLR_FLT
MAX_VM_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low (1)(MOSFETs in Hi-Z) Active Automatic:
(VVM < MAX_VM_MOTOR - VOLTAGE_HYSTERESIS) V
Minimum VPVDD (under-voltage) fault VPVDD < MIN_VM_MOTOR, if MIN_VM_MOTOR ≠ 000b MIN_VM_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low (1)(MOSFETs in Hi-Z) Active Latched:
CLR_FLT
MIN_VM_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low (1)(MOSFETs in Hi-Z) Active Automatic:
(VVM > MIN_VM_MOTOR + VOLTAGE_HYSTERESIS) V
Current Loop Saturation Indication of current loop saturation due to lower VVM SATURATION_FLAGS_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active; motor speed/power/current may not reach reference Active Automatic: motor will reach reference operating point upon exiting saturation
Speed/power Loop Saturation Indication of speed/power loop saturation due to lower VVM, lower ILIMIT setting etc., SATURATION_FLAGS_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active; motor speed/power may not reach reference Active Automatic: motor will reach reference operating point upon exiting saturation
External Watchdog Fault Time between watchdog tickles > EXT_WD_CONFIG EXT_WD_EN = 1bEXT_WD_FAULT_MODE = 0b and LIMP_HOME_EN = 0b nFAULT and CONTROLLER_FA ULT_STATUS register Active Active No action
EXT_WD_EN = 1bEXT_WD_FAULT_MODE = 0b and LIMP_HOME_EN = 1b nFAULT and CONTROLLER_FA ULT_STATUS register Active (reference latched at current value till CLR_FLT) Active Latched:
CLR_FLT
EXT_WD_EN = 1bEXT_WD_FAULT_MODE = 1b and LIMP_HOME_EN = 0b nFAULT and CONTROLLER_FA ULT_STATUS register Pulled Low (MOSFETs in Hi-Z) Active Latched:
CLR_FLT
EXT_WD_EN = 1bEXT_WD_FAULT_MODE = 1b and LIMP_HOME_EN = 1b nFAULT and CONTROLLER_FA ULT_STATUS register Active (reference latched at REF_OFF1) Active Latched:
CLR_FLT
EEPROM Fault Indicates EEPROM contents error/mismatch; content evaluation happens whenever a EEPROM read is issued EEP_FAULT_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low (MOSFETs in Hi-Z) Active Latched:
CLR_FLT
EEP_FAULT_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
I2C CRC Fault Indicates error in I2C transaction as a CRC mismatch I2C_CRC_ERR_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low (MOSFETs in Hi-Z) Active Latched:
CLR_FLT
I2C_CRC_ERR_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
Dry Run Detection Refer Section 7.3.23.14 DRY_RUN_MODE = 00b None Active Active No action
DRY_RUN_MODE = 01b nFAULT and CONTROLLER_FA ULT_STATUS register Active Active No action
DRY_RUN_MODE = 10b nFAULT and CONTROLLER_FA ULT_STATUS register Pulled Low (MOSFETs in Hi-Z) Active Retry:
tLCK_RETRY
DRY_RUN_MODE = 11b nFAULT and CONTROLLER_FA ULT_STATUS register Pulled Low (MOSFETs in Hi-Z) Active Latched:
CLR_FLT
Thermal shutdown
(TSD)		 TJ > TTSD OTS_AUTO_RECOVERY = 0b nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low (MOSFETs in Hi-Z) (1) Active Latched:
CLR_FLT
OTS_AUTO_RECOVERY = 1b nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low (MOSFETs in Hi-Z) (1) Active Automatic:
TJ < TOTSD – THYS
(1) Pulled Low: GHx and GLx are actively pulled low by the gate driver
Note: Any fault reporting on nFAULT pin or CONTROLLER_FAULT_STATUS register or GATE_DRIVER_FAULT_STATUS register can have a latency up to 200ms.