SBASB61 August   2026 ADS124S18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs and Multiplexer
      2. 7.3.2  Programmable Gain Amplifier (PGA)
      3. 7.3.3  Voltage Reference
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
        3. 7.3.3.3 Reference Buffers
      4. 7.3.4  Power-Scalable Speed Modes
      5. 7.3.5  Clock Source
      6. 7.3.6  Delta-Sigma Modulator
      7. 7.3.7  Digital Filter
        1. 7.3.7.1 Sinc3 and Sinc4 Filters
        2. 7.3.7.2 Sinc4 + Sinc1 Filter
        3. 7.3.7.3 FIR Filter
        4. 7.3.7.4 50Hz and 60Hz Line Cycle Rejection
        5. 7.3.7.5 Digital Filter Latency
        6. 7.3.7.6 Global-Chop Mode
      8. 7.3.8  Excitation Current Sources (IDACs)
      9. 7.3.9  Burn-Out Current Sources (BOCS)
      10. 7.3.10 Bias Voltage Generator (VBIAS)
      11. 7.3.11 General Purpose IOs (GPIOs)
        1. 7.3.11.1 ALERT Output
        2. 7.3.11.2 FAULT Output
      12. 7.3.12 Offset and Gain Calibration Coefficients
      13. 7.3.13 Digital Comparator
      14. 7.3.14 System Monitors
        1. 7.3.14.1 Internal Short (Offset Calibration)
        2. 7.3.14.2 Internal Temperature Sensor
        3. 7.3.14.3 External Reference Voltage Readback
        4. 7.3.14.4 Power-Supply Readback
      15. 7.3.15 Monitors and Status Flags
        1. 7.3.15.1 Reset (RESETn flag)
        2. 7.3.15.2 AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.15.3 Reference Undervoltage Monitor (REF_UVn flag)
        4. 7.3.15.4 SPI CRC Fault (SPI_CRC_FAULTn flag)
        5. 7.3.15.5 Register Map CRC Fault (REG_MAP_CRC_FAULTn flag)
        6. 7.3.15.6 Internal Memory Fault (MEM_FAULTn flag)
        7. 7.3.15.7 Register Write Fault (REG_WRITE_FAULTn flag)
        8. 7.3.15.8 Digital Comparator Alert (COMP_ALERTn flag)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-up and Reset
        1. 7.4.1.1 Power-On Reset (POR)
        2. 7.4.1.2 RESET Pin
        3. 7.4.1.3 Reset by Register Write
        4. 7.4.1.4 Reset by SPI Input Pattern
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Idle and Standby Mode
        2. 7.4.2.2 Power-Down Mode
        3. 7.4.2.3 Sequencer Mode
          1. 7.4.2.3.1 Configuring the Sequencer
          2. 7.4.2.3.2 Starting and Stopping the Sequencer (START/STOP bits and START pin)
          3. 7.4.2.3.3 Sequencer Status Bits
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No Operation (Read Conversion Data)
        2. 7.5.4.2 Read Register Command
        3. 7.5.4.3 Write Register Command
      5. 7.5.5  Continuous-Read Mode
        1. 7.5.5.1 Read Registers in Continuous-Read Mode
      6. 7.5.6  Daisy-Chain Operation
      7. 7.5.7  3-Wire SPI Mode
        1. 7.5.7.1 3-Wire SPI Mode Frame Re-Alignment
      8. 7.5.8  Monitoring for New Conversion Data
        1. 7.5.8.1 DRDY Pin or SDO/DRDY Pin Monitoring
        2. 7.5.8.2 Reading DRDY Bit and Conversion Counter
        3. 7.5.8.3 Clock Counting
      9. 7.5.9  DRDY Pin Behavior
      10. 7.5.10 Register Map CRC
      11. 7.5.11 Conversion Data Format
  9. 8 Register Map
    1. 8.1 Status and General Configuration Page Registers
    2. 8.2 Step Configuration Page Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Unused Inputs and Outputs
      3. 9.1.3 Interfacing With Multiple Devices
      4. 9.1.4 Device Initialization and Starting the Sequencer
      5. 9.1.5 Sequencer Configuration Strategy Example
    2. 9.2 Typical Applications
      1. 9.2.1 Software-Configurable RTD Measurement Input
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Performance Plots
        4. 9.2.1.4 Design Variant – 3-Wire RTD Measurement With Automatic Lead-Wire Compensation Using Two IDACs
      2. 9.2.2 Thermocouple Measurement With Cold-Junction Compensation Using a 2-wire RTD
      3. 9.2.3 Resistive Bridge Sensor Measurement With Temperature Compensation
      4. 9.2.4 Autonomous Power Supply Monitoring
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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7.4.2.3 Sequencer Mode

Conversions of the ADS1x4S1x are controlled by means of a sequencer together with the START and STOP bits or the START pin. The sequencer schedules conversions based on the sequencer mode configuration (SEQ_MODE[1:0] bit settings).

The devices offer up to 24 unique configuration settings (steps x = 0 to 23), which can be programmed during device initialization into the sequencer step configuration register pages. Each step configuration page allows the user to select device settings such as the input multiplexer, PGA gain, voltage reference source, digital filter type and OSR, excitation current source magnitude and routing, GPIO data output, and digital comparator thresholds. See the Step Configuration Page Registers section for details on all available configuration options per sequence step.

Table 7-19 describes how the SEQ_MODE[1:0] bits determine the sequencer operation when the host starts the sequencer.

Table 7-19 Sequencer Modes
SEQ_MODE[1:0] SEQUENCER OPERATION
00b The device executes the sequence step defined by the STEP_INIT[4:0] pointer one time. The step enable bits (STEP_x_EN) are ignored in this sequencer mode. The STEPx_NUM_CONV[4:0] bits determine the number of consecutive conversions that are performed for this sequence step. If STEPx_NUM_CONV[4:0] = 00000b, a single conversion is executed. This is commonly referred to as single-shot conversion mode in TI ADCs that do not offer a sequencer. After the number of conversions defined by the STEPx_NUM_CONV[4:0] bits are converted, the device returns to idle or standby mode, depending on the STBY_MODE bit setting. See Figure 7-20 for a detailed sequencer operation flow chart.
01b The device continuously converts the sequence step defined by the STEP_INIT[4:0] pointer. This is commonly referred to as continuous-conversion mode in TI ADCs that do not offer a sequencer. The step enable bits (STEP_x_EN) and STEPx_NUM_CONV[4:0] bits are ignored in this sequencer mode. Stop conversions by setting the STOP bit to 1b or by taking the START pin low. See Figure 7-21 for a detailed sequencer operation flow chart.
10b The device executes a sequence of all enabled steps between the step defined by the STEP_INIT[4:0] pointer and step 23 one time. Use the STEP_x_EN bits to include a step in the sequence. The sequence does not execute if the step defined by the STEP_INIT[4:0] pointer is disabled. After completing the conversions of the last enabled sequence step, the device returns to idle or standby mode, depending on the STBY_MODE bit setting. See Figure 7-22 for a detailed sequencer operation flow chart.
11b The device executes the complete sequence of enabled steps and repeats the sequence continuously, starting with the step defined by the STEP_INIT[4:0] pointer. After completing conversions of the last enabled step in the sequence, the device executes a new sequence run starting with the first enabled step. The first enabled step can be different from the step defined in the STEP_INIT[4:0] pointer. Use the STEP_x_EN bits to include a step in the sequence. The sequence does not execute if the step defined by the STEP_INIT[4:0] pointer is disabled. Stop the sequencer by setting the STOP bit to 1b or by taking the START pin low. See Figure 7-22 for a detailed sequencer operation flow chart.

Figure 7-20, Figure 7-21, and Figure 7-22 illustrate the sequencer behavior for the different sequencer modes. The flow charts show the behavior when using the START and STOP bits to control the sequencer. The START pin can be used instead as explained in the Starting and Stopping the Sequencer (START/STOP bits and START pin) section.

ADS114S14 ADS114S18 ADS124S14 ADS124S18 Sequencer Operation Flow Chart (SEQ_MODE[1:0] = 00b) Figure 7-20 Sequencer Operation Flow Chart (SEQ_MODE[1:0] = 00b)
ADS114S14 ADS114S18 ADS124S14 ADS124S18 Sequencer Operation Flow Chart (SEQ_MODE[1:0] = 01b) Figure 7-21 Sequencer Operation Flow Chart (SEQ_MODE[1:0] = 01b)
ADS114S14 ADS114S18 ADS124S14 ADS124S18 Sequencer Operation Flow Chart (SEQ_MODE[1:0] = 10b or 11b)(STOP_BEHAVIOR[1:0] = 01b) Figure 7-22 Sequencer Operation Flow Chart (SEQ_MODE[1:0] = 10b or 11b)
(STOP_BEHAVIOR[1:0] = 01b)