SBASB61 August   2026 ADS124S18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs and Multiplexer
      2. 7.3.2  Programmable Gain Amplifier (PGA)
      3. 7.3.3  Voltage Reference
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
        3. 7.3.3.3 Reference Buffers
      4. 7.3.4  Power-Scalable Speed Modes
      5. 7.3.5  Clock Source
      6. 7.3.6  Delta-Sigma Modulator
      7. 7.3.7  Digital Filter
        1. 7.3.7.1 Sinc3 and Sinc4 Filters
        2. 7.3.7.2 Sinc4 + Sinc1 Filter
        3. 7.3.7.3 FIR Filter
        4. 7.3.7.4 50Hz and 60Hz Line Cycle Rejection
        5. 7.3.7.5 Digital Filter Latency
        6. 7.3.7.6 Global-Chop Mode
      8. 7.3.8  Excitation Current Sources (IDACs)
      9. 7.3.9  Burn-Out Current Sources (BOCS)
      10. 7.3.10 Bias Voltage Generator (VBIAS)
      11. 7.3.11 General Purpose IOs (GPIOs)
        1. 7.3.11.1 ALERT Output
        2. 7.3.11.2 FAULT Output
      12. 7.3.12 Offset and Gain Calibration Coefficients
      13. 7.3.13 Digital Comparator
      14. 7.3.14 System Monitors
        1. 7.3.14.1 Internal Short (Offset Calibration)
        2. 7.3.14.2 Internal Temperature Sensor
        3. 7.3.14.3 External Reference Voltage Readback
        4. 7.3.14.4 Power-Supply Readback
      15. 7.3.15 Monitors and Status Flags
        1. 7.3.15.1 Reset (RESETn flag)
        2. 7.3.15.2 AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.15.3 Reference Undervoltage Monitor (REF_UVn flag)
        4. 7.3.15.4 SPI CRC Fault (SPI_CRC_FAULTn flag)
        5. 7.3.15.5 Register Map CRC Fault (REG_MAP_CRC_FAULTn flag)
        6. 7.3.15.6 Internal Memory Fault (MEM_FAULTn flag)
        7. 7.3.15.7 Register Write Fault (REG_WRITE_FAULTn flag)
        8. 7.3.15.8 Digital Comparator Alert (COMP_ALERTn flag)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-up and Reset
        1. 7.4.1.1 Power-On Reset (POR)
        2. 7.4.1.2 RESET Pin
        3. 7.4.1.3 Reset by Register Write
        4. 7.4.1.4 Reset by SPI Input Pattern
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Idle and Standby Mode
        2. 7.4.2.2 Power-Down Mode
        3. 7.4.2.3 Sequencer Mode
          1. 7.4.2.3.1 Configuring the Sequencer
          2. 7.4.2.3.2 Starting and Stopping the Sequencer (START/STOP bits and START pin)
          3. 7.4.2.3.3 Sequencer Status Bits
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No Operation (Read Conversion Data)
        2. 7.5.4.2 Read Register Command
        3. 7.5.4.3 Write Register Command
      5. 7.5.5  Continuous-Read Mode
        1. 7.5.5.1 Read Registers in Continuous-Read Mode
      6. 7.5.6  Daisy-Chain Operation
      7. 7.5.7  3-Wire SPI Mode
        1. 7.5.7.1 3-Wire SPI Mode Frame Re-Alignment
      8. 7.5.8  Monitoring for New Conversion Data
        1. 7.5.8.1 DRDY Pin or SDO/DRDY Pin Monitoring
        2. 7.5.8.2 Reading DRDY Bit and Conversion Counter
        3. 7.5.8.3 Clock Counting
      9. 7.5.9  DRDY Pin Behavior
      10. 7.5.10 Register Map CRC
      11. 7.5.11 Conversion Data Format
  9. 8 Register Map
    1. 8.1 Status and General Configuration Page Registers
    2. 8.2 Step Configuration Page Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Unused Inputs and Outputs
      3. 9.1.3 Interfacing With Multiple Devices
      4. 9.1.4 Device Initialization and Starting the Sequencer
      5. 9.1.5 Sequencer Configuration Strategy Example
    2. 9.2 Typical Applications
      1. 9.2.1 Software-Configurable RTD Measurement Input
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Performance Plots
        4. 9.2.1.4 Design Variant – 3-Wire RTD Measurement With Automatic Lead-Wire Compensation Using Two IDACs
      2. 9.2.2 Thermocouple Measurement With Cold-Junction Compensation Using a 2-wire RTD
      3. 9.2.3 Resistive Bridge Sensor Measurement With Temperature Compensation
      4. 9.2.4 Autonomous Power Supply Monitoring
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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9.2.4.2 Detailed Design Procedure

Monitoring a 3.3V rail while using a 3.3V AVDD supply for the ADS114S18 requires to attenuate the rail voltage before feeding the signal to the ADC inputs due to the device input voltage limitations. See the maximum absolute input voltage specification in the Recommended Operating Conditions table. To allow for margin in the design, the resistor divider values, R1 and R2, are chose such that at a 3.6V rail voltage the input signal at the analog input is less than 2.5V. In this configuration, the ADS114S18 can use gain = 1 and the internal 2.5V reference to measure rail voltages exceeding the overvoltage threshold of 3.5V. Using R1 = 50kΩ and R2 = 100kΩ sets the nominal ADC input voltage for a 3.3V rail to 2.2V. The 3.5V overvoltage threshold yields an input voltage of 2.33V, and the 3.1V undervoltage threshold and input voltage of 2.07V.

The device can measure the 1.8V and 1.2V rails directly using gain = 1 and the internal 2.5V reference without the need for any attenuation.

As a next step in the system design, calculate the digital comparator thresholds for the three rails. The design leverages the unipolar straight binary coding of the ADS114S18 because only positive input voltages need to be measured. With that, the LSB size using gain = 1 and the internal 2.5V reference calculates to:

Equation 39. LSB size = VREF / (Gain × 216) = 2.5V / 216 = 38.15μV

Use Equation 40 to calculate the digital comparator high and low threshold code values for the three rails.

Equation 40. Threshold Code = VThreshold / LSB size

As an example, set the digital comparator low threshold value for the 3.3V rail undervoltage detection to 2.07V / 38.15μV = 54176, which equates to a HEX code of D3A0h.

Next, select the sequencer operation. This example uses three sequence steps, one step for each supply rail measurement. Use sequencer mode SEQ_MODE[1:0] = 11b to implement an autonomous rail monitor that does not require any host interaction. This monitoring system example takes four consecutive measurements of each rail before switching to the next rail measurement. The comparator alert counter threshold is set to two so that two consecutive measurements on each step need to exceed the threshold before tripping the comparator.

The required speed mode and digital filter settings depend on the required fault detection time of the system.

Configure GPIO3 as an active-low, push-pull ALERT output as described in the ALERT Output section. In addition, add a pull-down resistor at the ALERT pin. This way, a low-level on the ALERT pin signals a supply fault to the host even when the ADS114S18 loses power or got reset, because GPIO3 reverts back to a High-Z input during device reset.

Table 9-4 summarizes the critical device register bit settings for this example.

Table 9-4 Supply Monitoring Register Bit Settings
REGISTER BITS SEQUENCE STEP 0
3.3V RAIL		 SEQUENCE STEP 1
1.8V RAIL		 SEQUENCE STEP 2
1.2V RAIL
Status and General Configuration Page
REF_VAL 1b (2.5V internal reference)
GPIO3_CFG[1:0] 10b (GPIO3 configured as push-pull digital output)
ALERT_PIN_POL 0b (ALERT output is active low)
GPIO3_SRC 1b (COMP_ALERTn flag controls the GPIO3 output)
SEQ_MODE[1:0] 11b (Sequencer continuously starts new sequence runs)
STEP_INIT[4:0] 00000b (Start initial sequence at sequence step 0)
STEP_x_EN STEP_0_EN = 1b STEP_1_EN = 1b STEP_2_EN = 1b
Step x Configuration Pages
STEPx_AINP[4:0] 00000b (AIN0) 00100b (AIN4) 01000b (AIN8)
STEPx_AINN[4:0] 10010b (Internal AVSS connection selected as negative input)
STEPx_REF_SEL[1:0] 00b (Internal voltage reference)
STEPx_GAIN[3:0] 0001b (Gain = 1)
STEPx_CODING 1b (Unipolar straight binary coding)
STEPx_NUM_CONV[4:0] 00011b (Four consecutive conversions per step)
STEPx_COMP_HIGH_TH[15:0] EEEFh (2.33V) Don't care Don't care
STEPx_COMP_LOW_TH[15:8] D3A0h (2.07V) AD0Eh (1.69V) 73B6h (1.13V)
STEPx_COMP_NUM[1:0] 01b (Two consecutive conversions exceeding the threshold trigger the digital comparator)
STEPx_COMP_HIGH_TH_EN 1b 0b 0b
STEPx_COMP_LOW_TH_EN 1b