SBASB61 August   2026 ADS124S18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs and Multiplexer
      2. 7.3.2  Programmable Gain Amplifier (PGA)
      3. 7.3.3  Voltage Reference
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
        3. 7.3.3.3 Reference Buffers
      4. 7.3.4  Power-Scalable Speed Modes
      5. 7.3.5  Clock Source
      6. 7.3.6  Delta-Sigma Modulator
      7. 7.3.7  Digital Filter
        1. 7.3.7.1 Sinc3 and Sinc4 Filters
        2. 7.3.7.2 Sinc4 + Sinc1 Filter
        3. 7.3.7.3 FIR Filter
        4. 7.3.7.4 50Hz and 60Hz Line Cycle Rejection
        5. 7.3.7.5 Digital Filter Latency
        6. 7.3.7.6 Global-Chop Mode
      8. 7.3.8  Excitation Current Sources (IDACs)
      9. 7.3.9  Burn-Out Current Sources (BOCS)
      10. 7.3.10 Bias Voltage Generator (VBIAS)
      11. 7.3.11 General Purpose IOs (GPIOs)
        1. 7.3.11.1 ALERT Output
        2. 7.3.11.2 FAULT Output
      12. 7.3.12 Offset and Gain Calibration Coefficients
      13. 7.3.13 Digital Comparator
      14. 7.3.14 System Monitors
        1. 7.3.14.1 Internal Short (Offset Calibration)
        2. 7.3.14.2 Internal Temperature Sensor
        3. 7.3.14.3 External Reference Voltage Readback
        4. 7.3.14.4 Power-Supply Readback
      15. 7.3.15 Monitors and Status Flags
        1. 7.3.15.1 Reset (RESETn flag)
        2. 7.3.15.2 AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.15.3 Reference Undervoltage Monitor (REF_UVn flag)
        4. 7.3.15.4 SPI CRC Fault (SPI_CRC_FAULTn flag)
        5. 7.3.15.5 Register Map CRC Fault (REG_MAP_CRC_FAULTn flag)
        6. 7.3.15.6 Internal Memory Fault (MEM_FAULTn flag)
        7. 7.3.15.7 Register Write Fault (REG_WRITE_FAULTn flag)
        8. 7.3.15.8 Digital Comparator Alert (COMP_ALERTn flag)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-up and Reset
        1. 7.4.1.1 Power-On Reset (POR)
        2. 7.4.1.2 RESET Pin
        3. 7.4.1.3 Reset by Register Write
        4. 7.4.1.4 Reset by SPI Input Pattern
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Idle and Standby Mode
        2. 7.4.2.2 Power-Down Mode
        3. 7.4.2.3 Sequencer Mode
          1. 7.4.2.3.1 Configuring the Sequencer
          2. 7.4.2.3.2 Starting and Stopping the Sequencer (START/STOP bits and START pin)
          3. 7.4.2.3.3 Sequencer Status Bits
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No Operation (Read Conversion Data)
        2. 7.5.4.2 Read Register Command
        3. 7.5.4.3 Write Register Command
      5. 7.5.5  Continuous-Read Mode
        1. 7.5.5.1 Read Registers in Continuous-Read Mode
      6. 7.5.6  Daisy-Chain Operation
      7. 7.5.7  3-Wire SPI Mode
        1. 7.5.7.1 3-Wire SPI Mode Frame Re-Alignment
      8. 7.5.8  Monitoring for New Conversion Data
        1. 7.5.8.1 DRDY Pin or SDO/DRDY Pin Monitoring
        2. 7.5.8.2 Reading DRDY Bit and Conversion Counter
        3. 7.5.8.3 Clock Counting
      9. 7.5.9  DRDY Pin Behavior
      10. 7.5.10 Register Map CRC
      11. 7.5.11 Conversion Data Format
  9. 8 Register Map
    1. 8.1 Status and General Configuration Page Registers
    2. 8.2 Step Configuration Page Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Unused Inputs and Outputs
      3. 9.1.3 Interfacing With Multiple Devices
      4. 9.1.4 Device Initialization and Starting the Sequencer
      5. 9.1.5 Sequencer Configuration Strategy Example
    2. 9.2 Typical Applications
      1. 9.2.1 Software-Configurable RTD Measurement Input
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Performance Plots
        4. 9.2.1.4 Design Variant – 3-Wire RTD Measurement With Automatic Lead-Wire Compensation Using Two IDACs
      2. 9.2.2 Thermocouple Measurement With Cold-Junction Compensation Using a 2-wire RTD
      3. 9.2.3 Resistive Bridge Sensor Measurement With Temperature Compensation
      4. 9.2.4 Autonomous Power Supply Monitoring
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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7.3.7.2 Sinc4 + Sinc1 Filter

STEPx_FLTR_OSR[4:0] bit settings 10001b to 11101b determine the OSR settings for the cascaded Sinc4 + Sinc1 filter path. The Sinc4 filter operates at a fixed OSR = 32 at those settings. The OSR settings of the Sinc1 filter range from 2 to 3200 to yield a combined OSR range from 64 to 102400. Compared to the Sinc3 or Sinc4 filter, the cascaded Sinc4 + Sinc1 filter path provides shorter settling time at the expense of degraded noise performance.

For STEPx_FLTR_OSR[4:0] bit settings 10001b to 11001b, Table 7-8 provides an overview of the resulting output data rates for the various speed modes based on the OSR setting. The data rates scale with fCLK.

Table 7-6 Sinc4 + Sinc1 Filter Output Data Rates
OSR –3dB Frequency OUTPUT DATA RATE (fDATA)(1)
SPEED MODE 0
(fMOD = 32kHz)		 SPEED MODE 1
(fMOD = 256kHz)		 SPEED MODE 2
(fMOD = 512kHz)		 SPEED MODE 3
(fMOD = 1.024MHz)
64 0.342× fDATA 500SPS 4kSPS 8kSPS 16kSPS
128 0.410× fDATA 250SPS 2kSPS 4kSPS 8kSPS
256 0.434× fDATA 125SPS 1kSPS 2kSPS 4kSPS
512 0.440× fDATA 62.5SPS 500SPS 1kSPS 2kSPS
640 0.441× fDATA 50SPS 400SPS 800SPS 1.6kSPS
1024 0.442× fDATA 31.25SPS 250SPS 500SPS 1kSPS
2048 0.442× fDATA 15.63SPS 125SPS 250SPS 500SPS
4096 0.442× fDATA 7.81SPS 62.5SPS 125SPS 250SPS
8192 0.442× fDATA 3.91SPS 31.25SPS 62.5SPS 125SPS
(1) Based on a nominal clock frequency of fCLK = 4.096MHz

For STEPx_FLTR_OSR[4:0] bit settings 11010b to 11101b, the device adjusts the OSR setting based on the selected speed mode to achieve the desired output data rates of 10SPS, 16.7SPS, 50SPS or 60SPS in each of the four speed modes. Table 7-7 lists the OSR settings for each speed mode. Because the output data rate scales with the clock frequency, use the internal oscillator or an external clock with a nominal frequency of fCLK = 4.096MHz to achieve the listed data rates.

The digital filter offers 50Hz line-cycle rejection at output data rates of 16.7SPS and 50SPS. At 60SPS, the digital filter offers 60Hz line-cycle rejection. The digital filter rejects both 50Hz and 60Hz line-cycle frequencies at 10SPS. See the 50Hz and 60Hz Line Cycle Rejection section for more details regarding the device's 50Hz and 60Hz line-cycle rejection capabilities.

Table 7-7 Sinc4 + Sinc1 Filter OSR Settings for Output Data Rates With Line-Cycle Rejection
OUTPUT DATA RATE(1)
(fDATA)		 –3dB Frequency OSR
SPEED MODE 0
(fMOD = 32kHz)		 SPEED MODE 1
(fMOD = 256kHz)		 SPEED MODE 2
(fMOD = 512kHz)		 SPEED MODE 3
(fMOD = 1.024MHz)
10SPS 4.4Hz 3200 25600 51200 102400
16.7SPS 7.4Hz 1920 15360 30720 61440
50SPS 22.1Hz 640 5120 10240 20480
60SPS 26.6Hz 544 4256 8544 17056
(1) Based on a nominal clock frequency of fCLK = 4.096MHz

The –3dB frequencies for the various Sinc filter configurations are given in Table 7-8 and Table 7-7.

The frequency response of the combined Sinc4 + Sinc1 filter is given by Equation 10.

Equation 10. ADS114S14 ADS114S18 ADS124S14 ADS124S18

where:

  • f = Signal frequency
  • fMOD = Modulator frequency
  • A = Sinc4 filter OSR = 32
  • B = Sinc1 filter OSR

Figure 7-5 and Figure 7-6 show examples of the filter frequency responses of the cascaded Sinc4 + Sinc1 filter normalized to the output data rate for Sinc1 OSRs of 4, 8, 16 and 32. A Sinc filter has infinite attenuation at integer multiples of the output data rate except for integer multiples of fMOD. As with all digital filters, the frequency response repeats at integer multiples of the modulator frequency, fMOD. The digital filter provides no attenuation at input frequencies near n × fMOD (n = 1, 2, 3, and so on). The data rate and filter notch frequencies scale with fMOD.

ADS114S14 ADS114S18 ADS124S14 ADS124S18 Sinc4 + Sinc1 Frequency Response(Sinc4 OSR = 32)Figure 7-5 Sinc4 + Sinc1 Frequency Response
(Sinc4 OSR = 32)
ADS114S14 ADS114S18 ADS124S14 ADS124S18 Sinc4 + Sinc1 Frequency Response(Sinc4 OSR = 32)Figure 7-6 Sinc4 + Sinc1 Frequency Response
(Sinc4 OSR = 32)