SBASB61 August   2026 ADS124S18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs and Multiplexer
      2. 7.3.2  Programmable Gain Amplifier (PGA)
      3. 7.3.3  Voltage Reference
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
        3. 7.3.3.3 Reference Buffers
      4. 7.3.4  Power-Scalable Speed Modes
      5. 7.3.5  Clock Source
      6. 7.3.6  Delta-Sigma Modulator
      7. 7.3.7  Digital Filter
        1. 7.3.7.1 Sinc3 and Sinc4 Filters
        2. 7.3.7.2 Sinc4 + Sinc1 Filter
        3. 7.3.7.3 FIR Filter
        4. 7.3.7.4 50Hz and 60Hz Line Cycle Rejection
        5. 7.3.7.5 Digital Filter Latency
        6. 7.3.7.6 Global-Chop Mode
      8. 7.3.8  Excitation Current Sources (IDACs)
      9. 7.3.9  Burn-Out Current Sources (BOCS)
      10. 7.3.10 Bias Voltage Generator (VBIAS)
      11. 7.3.11 General Purpose IOs (GPIOs)
        1. 7.3.11.1 ALERT Output
        2. 7.3.11.2 FAULT Output
      12. 7.3.12 Offset and Gain Calibration Coefficients
      13. 7.3.13 Digital Comparator
      14. 7.3.14 System Monitors
        1. 7.3.14.1 Internal Short (Offset Calibration)
        2. 7.3.14.2 Internal Temperature Sensor
        3. 7.3.14.3 External Reference Voltage Readback
        4. 7.3.14.4 Power-Supply Readback
      15. 7.3.15 Monitors and Status Flags
        1. 7.3.15.1 Reset (RESETn flag)
        2. 7.3.15.2 AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.15.3 Reference Undervoltage Monitor (REF_UVn flag)
        4. 7.3.15.4 SPI CRC Fault (SPI_CRC_FAULTn flag)
        5. 7.3.15.5 Register Map CRC Fault (REG_MAP_CRC_FAULTn flag)
        6. 7.3.15.6 Internal Memory Fault (MEM_FAULTn flag)
        7. 7.3.15.7 Register Write Fault (REG_WRITE_FAULTn flag)
        8. 7.3.15.8 Digital Comparator Alert (COMP_ALERTn flag)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-up and Reset
        1. 7.4.1.1 Power-On Reset (POR)
        2. 7.4.1.2 RESET Pin
        3. 7.4.1.3 Reset by Register Write
        4. 7.4.1.4 Reset by SPI Input Pattern
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Idle and Standby Mode
        2. 7.4.2.2 Power-Down Mode
        3. 7.4.2.3 Sequencer Mode
          1. 7.4.2.3.1 Configuring the Sequencer
          2. 7.4.2.3.2 Starting and Stopping the Sequencer (START/STOP bits and START pin)
          3. 7.4.2.3.3 Sequencer Status Bits
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No Operation (Read Conversion Data)
        2. 7.5.4.2 Read Register Command
        3. 7.5.4.3 Write Register Command
      5. 7.5.5  Continuous-Read Mode
        1. 7.5.5.1 Read Registers in Continuous-Read Mode
      6. 7.5.6  Daisy-Chain Operation
      7. 7.5.7  3-Wire SPI Mode
        1. 7.5.7.1 3-Wire SPI Mode Frame Re-Alignment
      8. 7.5.8  Monitoring for New Conversion Data
        1. 7.5.8.1 DRDY Pin or SDO/DRDY Pin Monitoring
        2. 7.5.8.2 Reading DRDY Bit and Conversion Counter
        3. 7.5.8.3 Clock Counting
      9. 7.5.9  DRDY Pin Behavior
      10. 7.5.10 Register Map CRC
      11. 7.5.11 Conversion Data Format
  9. 8 Register Map
    1. 8.1 Status and General Configuration Page Registers
    2. 8.2 Step Configuration Page Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Unused Inputs and Outputs
      3. 9.1.3 Interfacing With Multiple Devices
      4. 9.1.4 Device Initialization and Starting the Sequencer
      5. 9.1.5 Sequencer Configuration Strategy Example
    2. 9.2 Typical Applications
      1. 9.2.1 Software-Configurable RTD Measurement Input
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Performance Plots
        4. 9.2.1.4 Design Variant – 3-Wire RTD Measurement With Automatic Lead-Wire Compensation Using Two IDACs
      2. 9.2.2 Thermocouple Measurement With Cold-Junction Compensation Using a 2-wire RTD
      3. 9.2.3 Resistive Bridge Sensor Measurement With Temperature Compensation
      4. 9.2.4 Autonomous Power Supply Monitoring
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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7.3.7.5 Digital Filter Latency

When the sequencer selects a new sequence step for conversions, the digital filter resets and requires a certain amount of time to provide settled output data. This time is called the latency time. The ADS1x4S1x hide the unsettled data internally and only indicate when settled conversion data are available, by transitioning the DRDY pin low and setting the DRDY bit to 1b. The conversion period for the second and all subsequent conversions within a sequence step equals tDATA = 1 / fDATA = OSR / fMOD as shown in Figure 7-11.

ADS114S14 ADS114S18 ADS124S14 ADS124S18 Latency Time and Conversion Period Figure 7-11 Latency Time and Conversion Period
The first conversion of the first sequence step after starting or restarting the sequencer using the START bit or START pin has a latency of tL1 as shown in Figure 7-11. Latency time tL1 is measured from the CS rising edge of the register write frame where the START bit is set to 1b or the START pin rising edge, to the first DRDY falling edge. Because the CS signal in the SPI clock domain is latched by the digital filter logic running on the modulator clock domain, the latency times calculated using Equation 11 have an uncertainty of ±1 tMOD.

When operating the sequencer in mode SEQ_MOD[1:0] = 10b or 11b, the first conversion of the second and all subsequent sequence steps has a latency of tL2 as shown in Figure 7-11. Latency time tL2 is measured from the DRDY falling edge of the last conversion of the previous sequence step to the DRDY falling edge of the first conversion of the new sequence step as shown in Figure 7-11.

In addition, a per-step programmable delay time can be added to delay the start of the conversion cycle when the sequencer selects a new sequence step. This delay time allows for settling of external components, such as the voltage reference after exiting standby mode, or for additional settling time when the sequencer switches from one sequence step to the next one with a different device configuration. The delay time is only added before the first conversion of a sequence step as shown in Figure 7-11. Subsequent conversions within the sequence step are not delayed. Use the STEPx_DELAY[6:0] bits to configure individual delay times for each sequence step.

The time to complete the first conversion of the first sequence step after starting or restarting the sequencer follows Equation 11.

When using sequencer modes SEQ_MODE[1:0] = 10b or 11b, the time to complete the first conversion of the second and all subsequent sequence steps follows Equation 12.

Equation 11. tL1 = tSTBY_DELAY + tSTEPx_DELAY + tOVERHEAD + tSTEPx_LATENCY
Equation 12. tL2 = tSTEPx_DELAY + tSTEPx_LATENCY

where:

  • tSTEPx_LATENCY is the latency time provided in Table 7-10 and Table 7-11
  • tSTEPx_DELAY is the delay time determined by the STEPx_DELAY[6:0] bits
  • tSTBY_DELAY = 0 when starting the sequencer from idle mode (STBY_MODE = 0b).
    When starting the sequencer from standby mode (STBY_MODE = 1b), the device adds a speed-mode dependent delay time before the user-programmable delay time to allow internal circuits to wake-up:
    • tSTBY_DELAY = 5 tMOD (Speed Mode 0)
    • tSTBY_DELAY = 27 tMOD (Speed Mode 1, Speed Mode 2)
    • tSTBY_DELAY = 35 tMOD (Speed Mode 3)
  • tOVERHEAD = 11 tMOD

Table 7-10 Latency for Sinc Filters With OSR Settings
OSR LATENCY IN tMOD(1) (ABSOLUTE TIME(2))
SPEED MODE 0
(fMOD = 32kHz)		 SPEED MODE 1
(fMOD = 256kHz)		 SPEED MODE 2
(fMOD = 512kHz)		 SPEED MODE 3
(fMOD = 1.024MHz)
SINC4 FILTER (STEPx_FLTR_MODE = 0b, STEPx_FLTR_OSR[4:0] = 00000b to 01100b)
8 38 (1.188ms) 46 (0.180ms) 46 (0.090ms) 62 (0.061ms)
16 70 (2.188ms) 78 (0.305ms) 78 (0.152ms) 94 (0.092ms)
24 102 (3.188ms) 110 (0.430ms) 110 (0.215ms) 126 (0.123ms)
32 134 (4.188ms) 142 (0.555ms) 142 (0.277ms) 158 (0.154ms)
64 262 (8.188ms) 270 (1.055ms) 270 (0.527ms) 286 (0.279ms)
128 518 (16.19ms) 526 (2.055ms) 526 (1.027ms) 542 (0.529ms)
256 1030 (32.19ms) 1038 (4.055ms) 1038 (2.027ms) 1054 (1.029ms)
512 2054 (64.19ms) 2062 (8.055ms) 2062 (4.027ms) 2078 (2.029ms)
640 2566 (80.19ms) 2574 (10.05ms) 2574 (5.027ms) 2590 (2.529ms)
1024 4102 (128.2ms) 4110 (16.05ms) 4110 (8.027ms) 4126 (4.029ms)
2048 8198 (256.2ms) 8206 (32.05ms) 8206 (16.03ms) 8222 (8.029ms)
4096 16390 (512.2ms) 16398 (64.05ms) 16398 (32.03ms) 16414 (16.03ms)
8192 32774 (1024ms) 32782 (128.1ms) 32782 (64.03ms) 32798 (32.03ms)
SINC3 FILTER (STEPx_FLTR_MODE = 1b, STEPx_FLTR_OSR[4:0] = 00000b to 01100b)
8 30 (0.938ms) 38 (0.148ms) 38 (0.074ms) 54 (0.053ms)
16 54 (1.688ms) 62 (0.242ms) 62 (0.121ms) 78 (0.076ms)
24 78 (2.438ms) 86 (0.336ms) 86 (0.168ms) 102 (0.100ms)
32 102 (3.188ms) 110 (0.430ms) 110 (0.215ms) 126 (0.123ms)
64 198 (6.188ms) 206 (0.805ms) 206 (0.402ms) 222 (0.217ms)
128 390 (12.19ms) 398 (1.555ms) 398 (0.777ms) 414 (0.404ms)
256 774 (24.19ms) 782 (3.055ms) 782 (1.527ms) 798 (0.779ms)
512 1542 (48.19ms) 1550 (6.055ms) 1550 (3.027ms) 1566 (1.529ms)
640 1926 (60.19ms) 1934 (7.555ms) 1934 (3.777ms) 1950 (1.904ms)
1024 3078 (96.19ms) 3086 (12.05ms) 3086 (6.027ms) 3102 (3.029ms)
2048 6150 (192.2ms) 6158 (24.05ms) 6158 (12.03ms) 6174 (6.029ms)
4096 12294 (384.2ms) 12302 (48.05ms) 12302 (24.03ms) 12318 (12.03ms)
8192 24582 (768.2ms) 24590 (96.05ms) 24590 (48.03ms) 24606 (24.03ms)
SINC4 + SINC1 FILTER (STEPx_FLTR_OSR[4:0] = 10001b to 11001b)
64 166 (5.188ms) 174 (0.680ms) 174 (0.340ms) 190 (0.186ms)
128 230 (7.188ms) 238 (0.930ms) 238 (0.465ms) 254 (0.248ms)
256 358 (11.19ms) 366 (1.430ms) 366 (0.715ms) 382 (0.373ms)
512 614 (19.19ms) 622 (2.430ms) 622 (1.215ms) 638 (0.623ms)
640 742 (23.19ms) 750 (2.930ms) 750 (1.465ms) 766 (0.748ms)
1024 1126 (35.19ms) 1134 (4.430ms) 1134 (2.215ms) 1150 (1.123ms)
2048 2150 (67.19ms) 2158 (8.430ms) 2158 (4.215ms) 2174 (2.123ms)
4096 4198 (131.2ms) 4206 (16.43ms) 4206 (8.215ms) 4222 (4.123ms)
8192 8294 (259.2ms) 8302 (32.43ms) 8302 (16.21ms) 8318 (8.123ms)
(1) tMOD = 1 / fMOD.
(2) Based on a nominal clock frequency of fCLK = 4.096MHz.
Table 7-11 Latency for Sinc and FIR Filters With Fixed Data Rate Settings
OUTPUT DATA RATE LATENCY IN tMOD(1) (ABSOLUTE TIME(2))
SPEED MODE 0
(fMOD = 32kHz)		 SPEED MODE 1
(fMOD = 256kHz)		 SPEED MODE 2
(fMOD = 512kHz)		 SPEED MODE 3
(fMOD = 1.024MHz)
SINC4 FILTER (STEPx_FLTR_MODE = 0b, STEPx_FLTR_OSR[4:0] = 01101b to 10000b)
10SPS 2134 (66.69ms) 17038 (66.55ms) 34062 (66.53ms) 68126 (66.53ms)
16.7SPS 2566 (80.19ms) 20494 (80.05ms) 40974 (80.03ms) 81950 (80.03ms)
50SPS 7686 (240.2ms) 61454 (240.1ms) 122894 (240.0ms) 245790 (240.0ms)
60SPS 12806 (400.2ms) 102414 (400.1ms) 204814 (400.0ms) 409630 (400.0ms)
SINC3 FILTER (STEPx_FLTR_MODE = 1b, STEPx_FLTR_OSR[4:0] = 01101b to 10000b)
10SPS 1602 (50.06ms) 12782 (49.93ms) 25550 (49.90ms) 51102 (49.90ms)
16.7SPS 1926 (60.19ms) 15374 (60.05ms) 30734 (60.03ms) 61470 (60.03ms)
50SPS 5766 (180.2ms) 46094 (180.1ms) 92174 (180.0ms) 184350 (180.0ms)
60SPS 9606 (300.2ms) 76814 (300.1ms) 153614 (300.0ms) 307230 (300.0ms)
SINC4 + SINC1 FILTER (STEPx_FLTR_OSR[4:0] = 11010b to 11101b)
10SPS 646 (20.19ms) 4366 (17.05ms) 8654 (16.90ms) 17182 (16.78ms)
16.7SPS 742 (23.19ms) 5230 (20.43ms) 10350 (20.21ms) 20606 (20.12ms)
50SPS 2022 (63.2ms) 15470 (60.4ms) 30830 (60.2ms) 61566 (60.1ms)
60SPS 3302 (103.2ms) 25710 (100.4ms) 51310 (100.2ms) 102526 (100.1ms)
FIR FILTER (STEPx_FLTR_OSR[4:0] = 11110b to 11111b)
20SPS 1726 (53.94ms) 12934 (50.52ms) 25734 (50.26ms) 51350 (50.15ms)
25SPS 1406 (43.94ms) 10374 (40.52ms) 20614 (40.26ms) 41110 (40.15ms)
(1) tMOD = 1 / fMOD.
(2) Based on a nominal clock frequency of fCLK = 4.096MHz.