SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The goal of the basic high-level programming model is to introduce a top-down approach to users that need to configure the GPMC module.
Figure 12-104 and Table 12-192 through Table 12-193 show a programming model top-level diagram for the GPMC, and a description of each step. Each block of the diagram is described in one of the following sections through a set of registers to configure.
Step | Description |
---|---|
NOR Memory Type | See Table 12-194. |
NOR Chip-Select Configuration | See Table 12-195. |
NOR Timings Configuration | See Table 12-196. |
WAIT Pin Configuration | See Table 12-204. |
Enable Chip-Select | See Table 12-205. |
Step | Description |
---|---|
NAND Memory Type | See Table 12-199. |
NAND Chip-Select Configuration | See Table 12-200. |
Write Operations (Asynchronous) | See Table 12-201. |
Read Operations (Asynchronous) | See Table 12-201. |
ECC Engine | See Table 12-202. |
Prefetch and Write-Posting Engine | See Table 12-203. |
WAIT Pin Configuration | See Table 12-204. |
Enable Chip-Select | See Table 12-205. |