SPRUJ28C november   2021  – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation From Texas Instruments
    3.     Glossary
    4.     Support Resources
    5.     Export Control Notice
    6.     Release History
    7.     Trademarks
  3. 1 Introduction
    1. 1.1 Device Overview
      1. 1.1.1 Device Overview Feature List
      2. 1.1.2 Device Block Diagram
      3. 1.1.3 Modules Allocation and Instances within Device Domains
    2. 1.2 Module Descriptions
      1. 1.2.1  Arm Cortex-A72 Subsystem
      2. 1.2.2  Arm Cortex-R5F Processor
      3. 1.2.3  C71x DSP Subsystem
      4. 1.2.4  Graphics Processing Unit
      5. 1.2.5  Video Accelerator
      6. 1.2.6  Vision Pre-processing Accelerator
      7. 1.2.7  Depth and Motion Perception Accelerator
      8. 1.2.8  Navigator Subsystem
      9. 1.2.9  Region-based Address Translation Module
      10. 1.2.10 Data Routing Unit
      11. 1.2.11 Display Subsystem
      12. 1.2.12 Camera Subsystem
      13. 1.2.13 Shared D-PHY Transmitter
      14. 1.2.14 Multicore Shared Memory Controller
      15. 1.2.15 DDR Subsystem
      16. 1.2.16 General Purpose Input/Output Interface
      17. 1.2.17 Inter-Integrated Circuit Interface
      18. 1.2.18 Improved Inter-Integrated Circuit Interface
      19. 1.2.19 Multi-channel Serial Peripheral Interface
      20. 1.2.20 Universal Asynchronous Receiver/Transmitter
      21. 1.2.21 Peripheral Component Interconnect Express Subsystem
      22. 1.2.22 Universal Serial Bus (USB) Subsystem
      23. 1.2.23 SerDes
      24. 1.2.24 General Purpose Memory Controller with Error Location Module
      25. 1.2.25 Multimedia Card/Secure Digital Interface
      26. 1.2.26 Enhanced Capture Module
      27. 1.2.27 Enhanced Pulse-Width Modulation Module
      28. 1.2.28 Enhanced Quadrature Encoder Pulse Module
      29. 1.2.29 Controller Area Network
      30. 1.2.30 Audio Tracking Logic
      31. 1.2.31 Multi-channel Audio Serial Port
      32. 1.2.32 Timers
      33. 1.2.33 Internal Diagnostics Modules
      34. 1.2.34 Analog-to-Digital Converter
      35. 1.2.35 Gigabit Ethernet Switch
      36. 1.2.36 Octal Serial Peripheral Interface and HyperBus Memory Controller as a Flash Subsystem
      37. 1.2.37 Security Management Subsystem
    3. 1.3 Device Identification
  4. 2 Memory Maps
    1. 2.1 MAIN Memory Map
    2. 2.2 MCU Memory Map
    3. 2.3 WKUP Memory Map
    4. 2.4 Processors View Memory Map
      1. 2.4.1 COMPUTE_CLUSTER0 Memory Map
      2. 2.4.2 DMPAC0 Memory Map
      3. 2.4.3 R5FSS0 Memory Map
      4. 2.4.4 R5FSS1 Memory Map
      5. 2.4.5 MCU_NAVSS0 Memory Map
      6. 2.4.6 MCU_R5FSS0 Memory Map
      7. 2.4.7 MCU_SA3_SS0 Memory Map
      8. 2.4.8 WKUP_SMS0 Memory Map
    5. 2.5 Region-based Address Translation
  5. 3 System Interconnect
    1. 3.1 System Interconnect Overview
    2. 3.2 System Interconnect Functional Description
      1. 3.2.1 Quality of Service (QoS)
        1. 3.2.1.1  AEP_GPU_BXS464_WRAP0_QoS_Map
        2. 3.2.1.2  CODEC0_QoS_Map
        3. 3.2.1.3  CODEC1_QoS_Map
        4. 3.2.1.4  COMPUTE_CLUSTER0_QoS_Map
        5. 3.2.1.5  COMPUTE_CLUSTERHP0_QoS_Map
        6. 3.2.1.6  DEBUGSS_WRAP0_QoS_Map
        7. 3.2.1.7  DMPAC0_QoS_Map
        8. 3.2.1.8  DSS0_QoS_Map
        9. 3.2.1.9  MCU_NAVSS0_PROXY0_QoS_Map
        10. 3.2.1.10 MCU_NAVSS0_RINGACC0_QoS_Map
        11. 3.2.1.11 MCU_NAVSS0_SEC_PROXY0_QoS_Map
        12. 3.2.1.12 MCU_R5FSS0_QoS_Map
        13. 3.2.1.13 MCU_SA3_SS0_QoS_Map
        14. 3.2.1.14 MMCSD0_QoS_Map
        15. 3.2.1.15 MMCSD1_QoS_Map
        16. 3.2.1.16 NAVSS0_PROXY_0_QoS_Map
        17. 3.2.1.17 NAVSS0_SEC_PROXY_0_QoS_Map
        18. 3.2.1.18 PCIE0_QoS_Map
        19. 3.2.1.19 PCIE1_QoS_Map
        20. 3.2.1.20 PCIE2_QoS_Map
        21. 3.2.1.21 PCIE3_QoS_Map
        22. 3.2.1.22 R5FSS0_QoS_Map
        23. 3.2.1.23 R5FSS1_QoS_Map
        24. 3.2.1.24 R5FSS2_QoS_Map
        25. 3.2.1.25 SA2_UL0_QoS_Map
        26. 3.2.1.26 UFS0_QoS_Map
        27. 3.2.1.27 USB0_QoS_Map
        28. 3.2.1.28 VPAC0_QoS_Map
        29. 3.2.1.29 VPAC1_QoS_Map
        30. 3.2.1.30 VUSR_DUAL0_QoS_Map
        31. 3.2.1.31 WKUP_SMS0_QoS_Map
      2. 3.2.2 Route ID
      3. 3.2.3 Initiator-Side Security Controls (ISC)
        1. 3.2.3.1  Special System Level Priv-ID
        2. 3.2.3.2  A72SS0_CORE0_0 ISC Table
        3. 3.2.3.3  A72SS0_CORE1_0 ISC Table
        4. 3.2.3.4  A72SS0_CORE2_0 ISC Table
        5. 3.2.3.5  A72SS0_CORE3_0 ISC Table
        6. 3.2.3.6  A72SS1_CORE0_0 ISC Table
        7. 3.2.3.7  A72SS1_CORE1_0 ISC Table
        8. 3.2.3.8  A72SS1_CORE2_0 ISC Table
        9. 3.2.3.9  A72SS1_CORE3_0 ISC Table
        10. 3.2.3.10 AEP_GPU_BXS464_WRAP0 ISC Table
        11. 3.2.3.11 CODEC0 ISC Table
        12. 3.2.3.12 CODEC1 ISC Table
        13. 3.2.3.13 COMPUTE_CLUSTER0 ISC Table
        14. 3.2.3.14 COMPUTE_CLUSTER0_C71SS0_0 ISC Table
        15. 3.2.3.15 COMPUTE_CLUSTER0_C71SS1_0 ISC Table
        16. 3.2.3.16 COMPUTE_CLUSTER0_C71SS2_0 ISC Table
        17. 3.2.3.17 COMPUTE_CLUSTER0_C71SS3_0 ISC Table
        18. 3.2.3.18 COMPUTE_CLUSTERHP0 ISC Table
        19. 3.2.3.19 COMPUTE_CLUSTERHP0_A72SS0_CORE0_0 ISC Table
        20. 3.2.3.20 COMPUTE_CLUSTERHP0_A72SS0_CORE1_0 ISC Table
        21. 3.2.3.21 COMPUTE_CLUSTERHP0_C71SS0_0 ISC Table
        22. 3.2.3.22 COMPUTE_CLUSTERHP0_C71SS1_0 ISC Table
        23. 3.2.3.23 DEBUGSS_WRAP0 ISC Table
        24. 3.2.3.24 DMPAC0_DOF_0 ISC Table
        25. 3.2.3.25 DMPAC0_FOCO_0 ISC Table
        26. 3.2.3.26 DMPAC0_FOCO_1 ISC Table
        27. 3.2.3.27 DMPAC0_SDE_0 ISC Table
        28. 3.2.3.28 DSS0 ISC Table
        29. 3.2.3.29 LED0 ISC Table
        30. 3.2.3.30 MCU_NAVSS0_PROXY0 ISC Table
        31. 3.2.3.31 MCU_NAVSS0_RINGACC0 ISC Table
        32. 3.2.3.32 MCU_NAVSS0_SEC_PROXY0 ISC Table
        33. 3.2.3.33 MCU_R5FSS0 ISC Table
        34. 3.2.3.34 MCU_SA3_SS0 ISC Table
        35. 3.2.3.35 MMCSD0 ISC Table
        36. 3.2.3.36 MMCSD1 ISC Table
        37. 3.2.3.37 NAVSS0_PROXY_0 ISC Table
        38. 3.2.3.38 NAVSS0_RINGACC_0 ISC Table
        39. 3.2.3.39 NAVSS0_SEC_PROXY_0 ISC Table
        40. 3.2.3.40 PCIE0 ISC Table
        41. 3.2.3.41 PCIE1 ISC Table
        42. 3.2.3.42 PCIE2 ISC Table
        43. 3.2.3.43 PCIE3 ISC Table
        44. 3.2.3.44 R5FSS0 ISC Table
        45. 3.2.3.45 R5FSS1 ISC Table
        46. 3.2.3.46 R5FSS2 ISC Table
        47. 3.2.3.47 SA2_UL0 ISC Table
        48. 3.2.3.48 UFS0 ISC Table
        49. 3.2.3.49 USB0 ISC Table
        50. 3.2.3.50 VPAC0 ISC Table
        51. 3.2.3.51 VPAC1 ISC Table
        52. 3.2.3.52 WKUP_SMS0_HSM_CBASS_0 ISC Table
        53. 3.2.3.53 WKUP_SMS0_TIFS_CBASS_0 ISC Table
      4. 3.2.4 Firewalls (FW)
        1. 3.2.4.1 Peripheral Firewalls (FW)
          1. 3.2.4.1.1 Firewall Tables
          2. 3.2.4.1.2 Firewall Tables
          3. 3.2.4.1.3 Firewall Tables
          4. 3.2.4.1.4 Firewall Tables
        2. 3.2.4.2 Memory or Region-based Firewalls
          1. 3.2.4.2.1 Region Based Firewall Functional Description
          2. 3.2.4.2.2 Channelized Firewalls
            1. 3.2.4.2.2.1 Channelized Firewall Functional Description
      5. 3.2.5 Null Error Reporting
      6. 3.2.6 Initiator-Target Connections
  6. 4 Initialization
    1. 4.1 Initialization Overview
      1. 4.1.1 ROM Code Overview
      2. 4.1.2 Bootloader Modes
      3. 4.1.3 Terminology
    2. 4.2 Boot Process
      1. 4.2.1 MCU ROM Code Architecture
        1. 4.2.1.1 Main Module
        2. 4.2.1.2 X509 Module
        3. 4.2.1.3 Buffer Manager Module
        4. 4.2.1.4 Log and Trace Module
        5. 4.2.1.5 System Module
        6. 4.2.1.6 Protocol Module
        7. 4.2.1.7 Driver Module
      2. 4.2.2 SMS ROM Description
      3. 4.2.3 Boot Process Flow
      4. 4.2.4 MCU Only vs Normal Boot
    3. 4.3 Boot Mode Pins
      1. 4.3.1  MCU_BOOTMODE Pin Mapping
      2. 4.3.2  BOOTMODE Pin Mapping
        1. 4.3.2.1 Primary Boot Mode Selection
        2. 4.3.2.2 Backup Boot Mode Selection When MCU Only = 0
        3. 4.3.2.3 Primary Boot Mode Configuration
        4. 4.3.2.4 Backup Boot Mode Configuration
      3. 4.3.3  No-boot/Dev-boot Configuration
      4. 4.3.4  Hyperflash Boot Device Configuration
      5. 4.3.5  OSPI Boot Device Configuration
      6. 4.3.6  QSPI Boot Device Configuration
      7. 4.3.7  SPI Boot Device Configuration
      8. 4.3.8  xSPI Boot Device Configuration
      9. 4.3.9  I2C Boot Device Configuration
      10. 4.3.10 MMC/SD Card Boot Device Configuration
      11. 4.3.11 eMMC Boot Device Configuration
      12. 4.3.12 Ethernet Boot Device Configuration
      13. 4.3.13 USB Boot Device Configuration
      14. 4.3.14 PCIe Boot Device Configuration
      15. 4.3.15 UART Boot Device Configuration
      16. 4.3.16 Serial NAND Boot Device Configuration
      17. 4.3.17 PLL Configuration
        1. 4.3.17.1 MCU_PLL0, MCU_PLL2, Main PLL0, and Main PLL3
        2. 4.3.17.2 MCU_PLL1
        3. 4.3.17.3 Main PLL1
        4. 4.3.17.4 Main PLL2
        5. 4.3.17.5 HSDIV Values
        6. 4.3.17.6 214
    4. 4.4 Boot Parameter Tables
      1. 4.4.1  Common Header
      2. 4.4.2  PLL Setup
      3. 4.4.3  PCIe Boot Parameter Table
      4. 4.4.4  I2C Boot Parameter Table
      5. 4.4.5  OSPI/QSPI/SPI Boot Parameter Table
      6. 4.4.6  Ethernet Boot Parameter Table
      7. 4.4.7  USB Boot Parameter Table
      8. 4.4.8  MMCSD Boot Parameter Table
      9. 4.4.9  UART Boot Parameter Table
      10. 4.4.10 Hyperflash Boot Parameter Table
      11. 4.4.11 Serial NAND Boot Parameter Table
    5. 4.5 Boot Image Format
      1. 4.5.1 Overall Structure
      2. 4.5.2 X.509 Certificate
      3. 4.5.3 Organizational Identifier (OID)
      4. 4.5.4 X.509 Extensions Specific to Boot
        1. 4.5.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
        2. 4.5.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 4.5.5 Extended Boot Info Extension
        1. 4.5.5.1 Impact on HS Device
        2. 4.5.5.2 Extended Boot Info Details
        3. 4.5.5.3 Certificate / Component Types
        4. 4.5.5.4 Extended Boot Encryption Info
        5. 4.5.5.5 Component Ordering
        6. 4.5.5.6 Memory Load Sections Overlap with Executable Components
        7. 4.5.5.7 Device Type and Extended Boot Extension
      6. 4.5.6 Generating X.509 Certificates
        1. 4.5.6.1 Key Generation
          1. 4.5.6.1.1 Degenerate RSA Keys
        2. 4.5.6.2 Configuration Script
      7. 4.5.7 Image Data
    6. 4.6 Boot Modes
      1. 4.6.1 I2C Bootloader Operation
        1. 4.6.1.1 I2C Initialization Process
          1. 4.6.1.1.1 Block Size
          2. 4.6.1.1.2 251
        2. 4.6.1.2 I2C Loading Process
          1. 4.6.1.2.1 Loading a Boot Image From EEPROM
      2. 4.6.2 SPI Bootloader Operation
        1. 4.6.2.1 SPI Initialization Process
        2. 4.6.2.2 SPI Loading Process
      3. 4.6.3 QSPI Bootloader Operation
        1. 4.6.3.1 QSPI Initialization Process
        2. 4.6.3.2 QSPI Loading Process
      4. 4.6.4 OSPI Bootloader Operation
        1. 4.6.4.1 OSPI Initialization Process
        2. 4.6.4.2 OSPI Loading Process
      5. 4.6.5 PCIe Bootloader Operation
        1. 4.6.5.1 PCIe Initialization Process
        2. 4.6.5.2 PCIe Loading Process
      6. 4.6.6 Ethernet Bootloader Operation
        1. 4.6.6.1 Ethernet Initialization Process
        2. 4.6.6.2 Ethernet Loading Process
          1. 4.6.6.2.1 Ethernet Boot Data Formats
            1. 4.6.6.2.1.1 Limitations
            2. 4.6.6.2.1.2 BOOTP Request
              1. 4.6.6.2.1.2.1 MAC Header (DIX)
              2. 4.6.6.2.1.2.2 IPv4 Header
              3. 4.6.6.2.1.2.3 UDP Header
              4. 4.6.6.2.1.2.4 BOOTP Payload
              5. 4.6.6.2.1.2.5 TFTP
        3. 4.6.6.3 Ethernet Hand Over Process
      7. 4.6.7 USB Bootloader Operation
        1. 4.6.7.1 USB-Specific Attributes
          1. 4.6.7.1.1 DFU Device Mode
      8. 4.6.8 MMCSD Bootloader Operation
      9. 4.6.9 UART Bootloader Operation
        1. 4.6.9.1 Initialization Process
        2. 4.6.9.2 UART Loading Process
          1. 4.6.9.2.1 UART XMODEM
        3. 4.6.9.3 UART Hand-Over Process
    7. 4.7 Boot Memory Maps
      1. 4.7.1 Memory Layout/MPU
      2. 4.7.2 Global Memory Addresses Used by ROM Code
      3. 4.7.3 Memory Reserved by ROM Code
  7. 5 Device Configuration
    1. 5.1 Control Module (CTRL_MMR)
      1. 5.1.1 CTRL_MMR Overview
      2. 5.1.2 CTRL_MMR Functional Description
        1. 5.1.2.1 Register Partitions
        2. 5.1.2.2 CTRL_MMR Interrupts
      3. 5.1.3 Control Module Registers
    2. 5.2 Power
      1. 5.2.1 Power Management Overview
      2. 5.2.2 WKUP_PSC0 Device-Specific Information
      3. 5.2.3 Power Management Subsystems
        1. 5.2.3.1 POK, PRG_PP, and POR Modules
          1. 5.2.3.1.1 Power OK (POK) Modules
            1. 5.2.3.1.1.1 POK Overview
          2. 5.2.3.1.2 PoR/Reset Generator (PRG_PP) Modules
            1. 5.2.3.1.2.1 PRG / PRG_PP Overview
          3. 5.2.3.1.3 Power on Reset (POR) Module
            1. 5.2.3.1.3.1 POR Overview
          4. 5.2.3.1.4 Timing
          5. 5.2.3.1.5 Restrictions
          6. 5.2.3.1.6 PRG_PP Programming Model
        2. 5.2.3.2 Power Glitch Detect (PGD) Modules
        3. 5.2.3.3 Voltage and Thermal Manager (VTM)
          1. 5.2.3.3.1 VTM Overview
            1. 5.2.3.3.1.1 VTM Features
            2. 5.2.3.3.1.2 VTM Not Supported Features
          2. 5.2.3.3.2 VTM Functional Description
            1. 5.2.3.3.2.1 VTM Temperature Status and Thermal Management
              1. 5.2.3.3.2.1.1 10-bit Temperature Values Versus Temperature
            2. 5.2.3.3.2.2 VTM Temperature Driven Alerts and Interrupts
            3. 5.2.3.3.2.3 VTM ECC Aggregator
            4. 5.2.3.3.2.4 VTM Programming Model
              1. 5.2.3.3.2.4.1 VTM Maximum Temperature Outrange Alert
              2. 5.2.3.3.2.4.2 Sensors Programming Sequences
            5. 5.2.3.3.2.5 AVS-Class0
      4. 5.2.4 Dynamic Power Management
        1. 5.2.4.1 AVS Support
    3. 5.3 Reset
      1. 5.3.1 Reset Overview
      2. 5.3.2 Reset Modules
      3. 5.3.3 Reset Sources
      4. 5.3.4 Reset Status
      5. 5.3.5 Reset Control
      6. 5.3.6 BOOTMODE Pins
      7. 5.3.7 Reset Sequences
        1. 5.3.7.1 MCU_PORz Overview
        2. 5.3.7.2 MCU_PORz Sequence
        3. 5.3.7.3 MCU_RESETz Sequence
        4. 5.3.7.4 PORz Sequence
        5. 5.3.7.5 RESET_REQz Sequence
      8. 5.3.8 PLL Behavior on Reset
    4. 5.4 Clocking
      1. 5.4.1 Clocking Overview
      2. 5.4.2 Modules Controlled by PLL
      3. 5.4.3 Clock Mapping
      4. 5.4.4 Clock Inputs
        1. 5.4.4.1 Overview
        2. 5.4.4.2 Mapping of Clock Inputs
      5. 5.4.5 Clock Outputs
        1. 5.4.5.1 Observation Clock Pins
          1. 5.4.5.1.1 MCU_OBSCLK0 Pin
          2. 5.4.5.1.2 OBSCLK0, OBSCLK1, and OBSCLK2 Pins
        2. 5.4.5.2 System Clock Pins
          1. 5.4.5.2.1 MCU_SYSCLKOUT0
          2. 5.4.5.2.2 SYSCLKOUT0
      6. 5.4.6 Device Oscillators
        1. 5.4.6.1 Device Oscillators Integration
          1. 5.4.6.1.1 Oscillators with External Crystal
          2. 5.4.6.1.2 Internal RC Oscillator
        2. 5.4.6.2 Oscillator Clock Loss Detection
      7. 5.4.7 PLLs
        1. 5.4.7.1  WKUP and MCU Domains PLL Overview
        2. 5.4.7.2  MAIN Domain PLLs Overview
        3. 5.4.7.3  PLL Reference Clocks
          1. 5.4.7.3.1 PLLs in MCU Domain
          2. 5.4.7.3.2 PLLs in MAIN Domain
        4. 5.4.7.4  Generic PLL Overview
          1. 5.4.7.4.1 PLLs Output Clocks Parameters
            1. 5.4.7.4.1.1 PLLs Input Clocks
            2. 5.4.7.4.1.2 PLL Output Clocks
              1. 5.4.7.4.1.2.1 PLLTS16FFCLAFRAC2 Type Output Clocks
              2. 5.4.7.4.1.2.2 PLL Lock
              3. 5.4.7.4.1.2.3 HSDIVIDER
              4. 5.4.7.4.1.2.4 ICG Module
              5. 5.4.7.4.1.2.5 PLL Power Down
              6. 5.4.7.4.1.2.6 PLL Calibration
          2. 5.4.7.4.2 PLL Spread Spectrum Modulation Module
            1. 5.4.7.4.2.1 Definition of SSMOD
            2. 5.4.7.4.2.2 SSMOD Configuration
        5. 5.4.7.5  PLLs Device-Specific Information
          1. 5.4.7.5.1 SSMOD Related Bitfields Table
          2. 5.4.7.5.2 Clock Synthesis Inputs to the PLLs
          3. 5.4.7.5.3 Clock Output Parameter
          4. 5.4.7.5.4 Calibration Related Bitfields
        6. 5.4.7.6  PLL and PLL Controller Connection
        7. 5.4.7.7  System Clocks Operating Frequency Ranges
        8. 5.4.7.8  Recommended Clock and Control Signal Transition Behavior
        9. 5.4.7.9  Interface Clock Specifications
        10. 5.4.7.10 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
          1. 5.4.7.10.1 PLL Initialization
            1. 5.4.7.10.1.1 Kick Protection Mechanism
            2. 5.4.7.10.1.2 PLL Initialization to PLL Mode
            3. 5.4.7.10.1.3 PLL Programming Requirements
              1. 5.4.7.10.1.3.1 PLL Calibration Procedure
          2. 5.4.7.10.2 Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
    5. 5.5 Module Integration
      1. 5.5.1  ADC
        1. 5.5.1.1 ADC Unsupported Features
        2. 5.5.1.2 ADC Integration Details
      2. 5.5.2  ATL
        1. 5.5.2.1 ATL Unsupported Features
        2. 5.5.2.2 ATL Integration Details
      3. 5.5.3  CPSW2G
        1. 5.5.3.1 CPSW2G Unsupported Features
        2. 5.5.3.2 MCU_CPSW2G0 Integration Details
        3. 5.5.3.3 CPSW2G0 Integration Details
      4. 5.5.4  CSI_RX
        1. 5.5.4.1 CSI_RX Unsupported Features
        2. 5.5.4.2 CSI_RX Integration Details
      5. 5.5.5  CSI_TX
        1. 5.5.5.1 CSI_TX Unsupported Features
        2. 5.5.5.2 CSI_TX Integration Details
      6. 5.5.6  DCC
        1. 5.5.6.1 DCC Unsupported Features
        2. 5.5.6.2 DCC Integration Details
      7. 5.5.7  DMTIMER (Timer)
        1. 5.5.7.1 DMTIMER (Timer) Unsupported Features
        2. 5.5.7.2 DMTIMER (Timer) Integration Details
      8. 5.5.8  DPHY_RX
        1. 5.5.8.1 DPHY_RX Unsupported Features
        2. 5.5.8.2 DPHY_RX Integration Details
      9. 5.5.9  DPHY_TX
        1. 5.5.9.1 DPHY_TX Unsupported Features
        2. 5.5.9.2 DPHY_TX Integration Details
      10. 5.5.10 DSS/DSI
        1. 5.5.10.1 DSS Unsupported Features
        2. 5.5.10.2 DSI Unsupported Features
        3. 5.5.10.3 DSS/DSI Integration Details
          1. 5.5.10.3.1 DSS Pixel Clock Sourcing
      11. 5.5.11 eCAP
        1. 5.5.11.1 eCAP Unsupported Features
        2. 5.5.11.2 eCAP Integration Details
      12. 5.5.12 ePWM
        1. 5.5.12.1 ePWM Unsupported Features
        2. 5.5.12.2 ePWM Integration Details
      13. 5.5.13 ESM
        1. 5.5.13.1 ESM Unsupported Features
        2. 5.5.13.2 ESM Integration Details
      14. 5.5.14 FSS
        1. 5.5.14.1 FSS Unsupported Features
        2. 5.5.14.2 FSS Integration Details
      15. 5.5.15 GPIO
        1. 5.5.15.1 GPIO Unsupported Features
        2. 5.5.15.2 GPIO Integration Details
      16. 5.5.16 GPMC
        1. 5.5.16.1 GPMC Unsupported Features
        2. 5.5.16.2 GPMC Integration Details
      17. 5.5.17 GPU
        1. 5.5.17.1 GPU Unsupported Features
        2. 5.5.17.2 GPU Integration Details
      18. 5.5.18 I2C
        1. 5.5.18.1 WKUP_I2C0 Unsupported Features
        2. 5.5.18.2 MCU_I2C[1:0] Unsupported Features
        3. 5.5.18.3 I2C[6:0] Unsupported Features
        4. 5.5.18.4 I2C Integration Details
      19. 5.5.19 I3C
        1. 5.5.19.1 I3C Unsupported Features
        2. 5.5.19.2 I3C Integration Details
      20. 5.5.20 MCAN
        1. 5.5.20.1 MCAN Unsupported Features
        2. 5.5.20.2 MCAN Integration Details
      21. 5.5.21 MMCSD
        1. 5.5.21.1 MMCSD Unsupported Features
        2. 5.5.21.2 MMCSD Integration Details
      22. 5.5.22 McASP
        1. 5.5.22.1 McASP Unsupported Features
        2. 5.5.22.2 McASP Integration Details
      23. 5.5.23 McSPI
        1. 5.5.23.1 MCSPI Unsupported Features
        2. 5.5.23.2 MCSPI Integration Details
      24. 5.5.24 PCIE
        1. 5.5.24.1 PCIE Unsupported Features
        2. 5.5.24.2 PCIE Integration Details
      25. 5.5.25 R5FSS
        1. 5.5.25.1 R5FSS and MCU_R5FSS Unsupported Features
        2. 5.5.25.2 MCU_R5FSS Integration Details
        3. 5.5.25.3 R5FSS Integration Details
      26. 5.5.26 RAT
        1. 5.5.26.1 RAT Integration Details
          1. 5.5.26.1.1 RAT Source IDs
      27. 5.5.27 RTI
        1. 5.5.27.1 RTI Unsupported Features
        2. 5.5.27.2 RTI Integration Details
      28. 5.5.28 UART
        1. 5.5.28.1 UART Unsupported Features
        2. 5.5.28.2 UART Integration Details
      29. 5.5.29 USBSS
        1. 5.5.29.1 USB Unsupported Features
        2. 5.5.29.2 USB Integration Details
      30. 5.5.30 Video CODEC
        1. 5.5.30.1 CODEC Unsupported Features
        2. 5.5.30.2 CODEC Integration Details
      31. 5.5.31 VPAC
        1. 5.5.31.1 VPAC Unsupported Features
        2. 5.5.31.2 VPAC Integration Details
  8. 6 Processors and Accelerators
    1. 6.1 Compute Cluster
      1. 6.1.1 Compute Cluster Overview
      2. 6.1.2 Compute Cluster Functional Description
        1. 6.1.2.1 Compute Cluster Memory Regions
        2. 6.1.2.2 Compute Cluster Firewalls
        3. 6.1.2.3 Compute Cluster ECC Aggregators
    2. 6.2 Dual-A72 MPU Subsystem
      1. 6.2.1 A72SS Overview
        1. 6.2.1.1 A72SS Introduction
        2. 6.2.1.2 A72SS Features
      2. 6.2.2 A72SS Functional Description
        1. 6.2.2.1  A72SS Block Diagram
        2. 6.2.2.2  A72SS A72 Cluster
        3. 6.2.2.3  A72SS Interfaces and Async Bridges
        4. 6.2.2.4  A72SS Interrupts
          1. 6.2.2.4.1 A72SS Interrupt Inputs
          2. 6.2.2.4.2 A72SS Interrupt Outputs
        5. 6.2.2.5  A72SS Power Management, Clocking and Reset
          1. 6.2.2.5.1 A72SS Power Management
          2. 6.2.2.5.2 A72SS Clocking
        6. 6.2.2.6  A72SS Debug Support
        7. 6.2.2.7  A72SS Timestamps
        8. 6.2.2.8  A72SS Watchdog
        9. 6.2.2.9  A72SS Internal Diagnostics
          1. 6.2.2.9.1 A72SS ECC Aggregators During Low Power States
          2. 6.2.2.9.2 A72SS CBASS Diagnostics
          3. 6.2.2.9.3 A72SS SRAM Diagnostics
          4. 6.2.2.9.4 A72SS SRAM ECC Aggregator Configurations
        10. 6.2.2.10 A72SS Cache Pre-Warming
        11. 6.2.2.11 A72SS Boot
        12. 6.2.2.12 A72SS IPC with Other CPUs
    3. 6.3 Dual-R5F MCU Subsystem
      1. 6.3.1 R5FSS Overview
        1. 6.3.1.1 R5FSS Features
      2. 6.3.2 R5FSS Functional Description
        1. 6.3.2.1  R5FSS Block Diagram
        2. 6.3.2.2  R5FSS Cortex-R5F Core
          1. 6.3.2.2.1 L1 Caches
          2. 6.3.2.2.2 Tightly-Coupled Memories (TCMs)
          3. 6.3.2.2.3 R5FSS Special Signals
        3. 6.3.2.3  R5FSS Interfaces
          1. 6.3.2.3.1 R5FSS Master Interfaces
          2. 6.3.2.3.2 R5FSS Slave Interfaces
        4. 6.3.2.4  R5FSS Power, Clocking and Reset
          1. 6.3.2.4.1 R5FSS Power
          2. 6.3.2.4.2 R5FSS Clocking
            1. 6.3.2.4.2.1 Changing MCU_R5FSS0 CPU Clock Frequency
          3. 6.3.2.4.3 R5FSS Reset
        5. 6.3.2.5  R5FSS Lockstep Error Detection Logic
          1. 6.3.2.5.1 CPU Output Compare Block
            1. 6.3.2.5.1.1 Operating Modes
            2. 6.3.2.5.1.2 Compare Block Active Mode
            3. 6.3.2.5.1.3 Self Test Mode
            4. 6.3.2.5.1.4 Compare Match Test
            5. 6.3.2.5.1.5 Compare Mismatch Test
            6. 6.3.2.5.1.6 Error Forcing Mode
            7. 6.3.2.5.1.7 Self Test Error Forcing Mode
          2. 6.3.2.5.2 Inactivity Monitor Block
            1. 6.3.2.5.2.1 Operating Modes
            2. 6.3.2.5.2.2 Compare Block Active Mode
            3. 6.3.2.5.2.3 Self Test Mode
            4. 6.3.2.5.2.4 Compare Match Test
            5. 6.3.2.5.2.5 Compare Mismatch Test
            6. 6.3.2.5.2.6 Error Forcing Mode
            7. 6.3.2.5.2.7 Self Test Error Forcing Mode
          3. 6.3.2.5.3 Polarity Inversion Logic
        6. 6.3.2.6  R5FSS Vectored Interrupt Manager (VIM)
          1. 6.3.2.6.1 VIM Overview
          2. 6.3.2.6.2 VIM Interrupt Inputs
          3. 6.3.2.6.3 VIM Interrupt Outputs
          4. 6.3.2.6.4 VIM Interrupt Vector Table (VIM RAM)
          5. 6.3.2.6.5 VIM Interrupt Prioritization
          6. 6.3.2.6.6 VIM ECC Support
          7. 6.3.2.6.7 VIM Lockstep Mode
          8. 6.3.2.6.8 VIM IDLE State
          9. 6.3.2.6.9 VIM Interrupt Handling
            1. 6.3.2.6.9.1 Servicing IRQ Through Vector Interface
            2. 6.3.2.6.9.2 Servicing IRQ Through MMR Interface
            3. 6.3.2.6.9.3 Servicing IRQ Through MMR Interface (Alternative)
            4. 6.3.2.6.9.4 Servicing FIQ
            5. 6.3.2.6.9.5 Servicing FIQ (Alternative)
        7. 6.3.2.7  R5FSS Region Address Translation (RAT)
          1. 6.3.2.7.1 RAT Overview
          2. 6.3.2.7.2 RAT Operation
          3. 6.3.2.7.3 RAT Error Logging
          4. 6.3.2.7.4 RAT Protection
        8. 6.3.2.8  R5FSS ECC Support
        9. 6.3.2.9  R5FSS Memory View
        10. 6.3.2.10 R5FSS Debug and Trace
        11. 6.3.2.11 R5FSS Boot Options
        12. 6.3.2.12 R5FSS Core Memory ECC Events
    4. 6.4 C71x DSP Subsystem
      1. 6.4.1 C71SS Overview
        1. 6.4.1.1 C71SS Features
      2. 6.4.2 C71SS Functional Description
        1. 6.4.2.1 C71x DSP CPU
        2. 6.4.2.2 C71x DSP Matrix Multiply Accelerator
        3. 6.4.2.3 C71x DSP Cache Memory System
          1. 6.4.2.3.1 C71x DSP L1 Program Memory
          2. 6.4.2.3.2 C71x DSP L1 Data Memory
          3. 6.4.2.3.3 C71x DSP L2 Memory
        4. 6.4.2.4 C71x DSP Streaming Engine
        5. 6.4.2.5 C71x DSP CorePac Memory Management Unit
        6. 6.4.2.6 C71x DSP ECC Support
        7. 6.4.2.7 C71x DSP Boot Configuration
        8. 6.4.2.8 C71x DSP Power-Up/Down Sequences
        9. 6.4.2.9 C71x DSP Interrupt Control
    5. 6.5 Graphics Accelerator (GPU)
      1. 6.5.1 GPU Overview
      2. 6.5.2 Features Supported
    6. 6.6 Video Accelerator
      1. 6.6.1 Introduction
      2. 6.6.2 Features
        1. 6.6.2.1 Performance
        2. 6.6.2.2 Codec Related Features
        3. 6.6.2.3 Non-Codec Related Features
      3. 6.6.3 Block Diagram
    7. 6.7 Vision Pre-processing Accelerator (VPAC)
      1. 6.7.1 VPAC Overview
        1. 6.7.1.1 VPAC Features
      2. 6.7.2 VPAC Subsystem Level
        1. 6.7.2.1  VPAC Subsystem Block Diagram
          1. 6.7.2.1.1 Notes on VISS RFE H3A Usage
        2. 6.7.2.2  VPAC Subsystem Clocks
        3. 6.7.2.3  VPAC Subsystem Resets
        4. 6.7.2.4  VPAC Subsystem Interrupts
        5. 6.7.2.5  VPAC Subsystem SL2 Memory Infrastructure
        6. 6.7.2.6  VPAC Subsystem DMA Infrastructure
        7. 6.7.2.7  VPAC Subsystem Data Routing Interconnect
        8. 6.7.2.8  VPAC Subsystem Pipeline Flow Control and Messaging
          1. 6.7.2.8.1 VISS Node Scheduler
          2. 6.7.2.8.2 LDC Node Scheduler
          3. 6.7.2.8.3 MSC Node Scheduler
          4. 6.7.2.8.4 NF Node Scheduler
          5. 6.7.2.8.5 Spare Scheduler
        9. 6.7.2.9  VPAC Subsystem Data Formats Support
        10. 6.7.2.10 VPAC Subsystem Debug Features
        11. 6.7.2.11 VPAC Subsystem Internal Diagnostic Features
          1. 6.7.2.11.1 Parallel Signature Analysis (PSA)
        12. 6.7.2.12 VPAC Subsystem Security Features
        13. 6.7.2.13 VPAC Subsystem Programmer’s Guide
          1. 6.7.2.13.1 Initialization Sequence
          2. 6.7.2.13.2 VISS Configuration
            1. 6.7.2.13.2.1 VISS UTC Configuration
            2. 6.7.2.13.2.2 VISS HTS Configuration for Line Mode
            3. 6.7.2.13.2.3 VISS HTS Configuration for Frame Mode
          3. 6.7.2.13.3 VISS OTF Configuration
          4. 6.7.2.13.4 LDC Configuration (LDC Connected to MSC0, NF and DMA)
            1. 6.7.2.13.4.1 LDC DMA Configuration
            2. 6.7.2.13.4.2 LDC HTS Configuration
          5. 6.7.2.13.5 Real-time Operating Requirements
      3. 6.7.3 VPAC Vision Imaging Subsystem (VISS)
        1. 6.7.3.1 VISS Top Level
          1. 6.7.3.1.1  Features Supported
          2. 6.7.3.1.2  VISS Block Diagram
          3. 6.7.3.1.3  VISS Data Flow within VPAC
            1. 6.7.3.1.3.1 VISS On-the-fly Processing
              1. 6.7.3.1.3.1.1 Non-WDR or Companded WDR Sensors
            2. 6.7.3.1.3.2 VISS Memory to Memory Image Processing
          4. 6.7.3.1.4  Concurret Machine Vision and Human Vision Output
          5. 6.7.3.1.5  VISS Clocking
          6. 6.7.3.1.6  VISS Data Formats Support
          7. 6.7.3.1.7  VISS VPORT Interface
          8. 6.7.3.1.8  VISS Submodule Integration Specifics
            1. 6.7.3.1.8.1 LSE Integration
            2. 6.7.3.1.8.2 Chromatic Aberration Correction
            3. 6.7.3.1.8.3 Spatial Noise Filter (NSF4V)
            4. 6.7.3.1.8.4 GLBCE Integration
              1. 6.7.3.1.8.4.1 GLBCE Startup
              2. 6.7.3.1.8.4.2 GLBCE Bypass
            5. 6.7.3.1.8.5 Flexible Color Processing (FCP)
          9. 6.7.3.1.9  VISS Stall Handling
          10. 6.7.3.1.10 VISS Blanking Requirements
          11. 6.7.3.1.11 FCP2 Sync FIFO
          12. 6.7.3.1.12 VISS Interrupts
            1. 6.7.3.1.12.1 Interrupts Merging
            2. 6.7.3.1.12.2 Handling of Configuration Error Interrupts
          13. 6.7.3.1.13 VISS Error Correcting Code (ECC) Support
          14. 6.7.3.1.14 VISS Programmer's Guide
            1. 6.7.3.1.14.1 VISS Initialization Sequence
            2. 6.7.3.1.14.2 VISS Configuration Restrictions
            3. 6.7.3.1.14.3 VISS Real-time Operating Requirements
        2. 6.7.3.2 VISS RAW Frond-End (RAWFE)
          1. 6.7.3.2.1 RAWFE Overview
            1. 6.7.3.2.1.1 RAWFE Supported Features
            2. 6.7.3.2.1.2 RAWFE Not Supported Features
          2. 6.7.3.2.2 RAWFE Functional Description
            1. 6.7.3.2.2.1 RAWFE Functional Operation
            2. 6.7.3.2.2.2 RAWFE Integration in VISS
            3. 6.7.3.2.2.3 RAWFE Memory Map
            4. 6.7.3.2.2.4 RAWFE ECC for RAMs
          3. 6.7.3.2.3 RAWFE Interrupts
            1. 6.7.3.2.3.1 RAWFE CPU Interrupts
            2. 6.7.3.2.3.2 RAWFE Debug Events
            3. 6.7.3.2.3.3 RAWFE Interrupt Handling: High Priority
            4. 6.7.3.2.3.4 RAWFE Interrupt Handling: Low Priority
          4. 6.7.3.2.4 RAWFE Sub-Modules Details
            1. 6.7.3.2.4.1 RAWFE Decompanding Block
              1. 6.7.3.2.4.1.1 RAWFE Mask & Shift
              2. 6.7.3.2.4.1.2 RAWFE Piece Wise Linear Operation
              3. 6.7.3.2.4.1.3 RAWFE Offset/WB-1 Block
              4. 6.7.3.2.4.1.4 RAWFE LUT Based compression
            2. 6.7.3.2.4.2 RAWFE WDR Merge Block
              1. 6.7.3.2.4.2.1 RAWFE WDR Motion Adaptive Merge (MA1 / MA2)
              2. 6.7.3.2.4.2.2 RAWFE Companding LUT
            3. 6.7.3.2.4.3 RAWFE Defective Pixel Correction (DPC) Block
              1. 6.7.3.2.4.3.1 RAWFE LUT Based DPC
              2. 6.7.3.2.4.3.2 RAWFE On-The-Fly (OTF) DPC
            4. 6.7.3.2.4.4 RAWFE Lens Shading Correction (LSC) and Digital Gain (DG) Block
              1. 6.7.3.2.4.4.1 RAWFE LSC Features Supported
              2. 6.7.3.2.4.4.2 RAWFE LSC Image Framing with Respect to Gain Map Samples
            5. 6.7.3.2.4.5 RAWFE Gain & Offset Block
            6. 6.7.3.2.4.6 RAWFE H3A
              1. 6.7.3.2.4.6.1  RAWFE H3A Overview
              2. 6.7.3.2.4.6.2  RAWFE H3A Top-Level Block Diagram
              3. 6.7.3.2.4.6.3  RAWFE H3A Line Framing Logic
              4. 6.7.3.2.4.6.4  RAWFE H3A Optional Preprocessing
              5. 6.7.3.2.4.6.5  RAWFE H3A Autofocus Engine
                1. 6.7.3.2.4.6.5.1 RAWFE H3A Paxel Extraction
                2. 6.7.3.2.4.6.5.2 RAWFE H3A Horizontal FV Calculator
                3. 6.7.3.2.4.6.5.3 RAWFE H3A HFV Accumulator
                4. 6.7.3.2.4.6.5.4 RAWFE H3A VFV Calculator
                5. 6.7.3.2.4.6.5.5 RAWFE H3A VFV Accumulator
              6. 6.7.3.2.4.6.6  RAWFE H3A AE/AWB Engine
                1. 6.7.3.2.4.6.6.1 RAWFE H3A Subsampler
                2. 6.7.3.2.4.6.6.2 RAWFE H3A Additional Black Row of AE/AWB Windows
                3. 6.7.3.2.4.6.6.3 RAWFE H3A Saturation Check
                4. 6.7.3.2.4.6.6.4 RAWFE H3A AE/AWB Accumulators
              7. 6.7.3.2.4.6.7  RAWFE H3A DMA Interface
              8. 6.7.3.2.4.6.8  RAWFE H3A Events and Status Checking
              9. 6.7.3.2.4.6.9  RAWFE H3A Interface Mux
              10. 6.7.3.2.4.6.10 RAWFE H3A interface to LSE
              11. 6.7.3.2.4.6.11 RAWFE H3A Erratas
          5. 6.7.3.2.5 RAWFE Programmer’s Guide
            1. 6.7.3.2.5.1 RAWFE Core programming details
            2. 6.7.3.2.5.2 RAWFE HTS programming details
            3. 6.7.3.2.5.3 RAWFE Data transfer programming details
            4. 6.7.3.2.5.4 RAWFE Initialization Sequence
            5. 6.7.3.2.5.5 RAWFE Real-time Оperating Requirements
            6. 6.7.3.2.5.6 RAWFE Power up/down Sequence
        3. 6.7.3.3 Chromatic Aberration Correction (CAC) Module
          1. 6.7.3.3.1 Overview and Feature List
            1. 6.7.3.3.1.1 Features Supported
          2. 6.7.3.3.2 Functional Description
            1. 6.7.3.3.2.1 CAC Integration in VISS
            2. 6.7.3.3.2.2 Introduction
            3. 6.7.3.3.2.3 Functional Operation
              1. 6.7.3.3.2.3.1 CAC Back Mapping
                1. 6.7.3.3.2.3.1.1 Offset Table Storage Format
              2. 6.7.3.3.2.3.2 Pixel Interpolation
              3. 6.7.3.3.2.3.3 Bi-cubic Coefficients
            4. 6.7.3.3.2.4 Interrupt Conditions
              1. 6.7.3.3.2.4.1 Interrupts
              2. 6.7.3.3.2.4.2 Debug Events
        4. 6.7.3.4 VISS Spatial Noise Filter (NSF4V)
          1. 6.7.3.4.1 NSF4V Introduction
            1. 6.7.3.4.1.1 NSF4V Features
          2. 6.7.3.4.2 NSF4V Overview
            1. 6.7.3.4.2.1 Decomposition Kernel Representation
          3. 6.7.3.4.3 NSF4V Lens Shading Correction Compensation
          4. 6.7.3.4.4 NSF4V Noise Threshold Adaptation to Local Image Intensity
          5. 6.7.3.4.5 Delta Features
        5. 6.7.3.5 VISS Global/Local Brightness and Contrast Enhancement (GLBCE) Module
          1. 6.7.3.5.1 GLBCE Overview
          2. 6.7.3.5.2 GLBCE Interface
          3. 6.7.3.5.3 GLBCE Core
            1. 6.7.3.5.3.1 GLBCE Core Key Parameters
            2. 6.7.3.5.3.2 GLBCE Iridix Strength Calculation
            3. 6.7.3.5.3.3 GLBCE Iridix Configuration Registers
              1. 6.7.3.5.3.3.1  GLBCE Iridix Frame Width
              2. 6.7.3.5.3.3.2  GLBCE Iridix Frame Height
              3. 6.7.3.5.3.3.3  GLBCE Iridix Control 0
              4. 6.7.3.5.3.3.4  GLBCE Iridix Control 1
              5. 6.7.3.5.3.3.5  GLBCE Iridix Strength
              6. 6.7.3.5.3.3.6  GLBCE Iridix Variance
              7. 6.7.3.5.3.3.7  GLBCE Iridix Dither
              8. 6.7.3.5.3.3.8  GLBCE Iridix Amplification Limit
              9. 6.7.3.5.3.3.9  GLBCE Iridix Slope Min and Max
              10. 6.7.3.5.3.3.10 GLBCE Iridix Black Level
              11. 6.7.3.5.3.3.11 GLBCE Iridix White Level
              12. 6.7.3.5.3.3.12 GLBCE Iridix Asymmetry Function Look-up-table
              13. 6.7.3.5.3.3.13 GLBCE Iridix Forward and Reverse Perceptual Functions Look-up-tables
              14. 6.7.3.5.3.3.14 GLBCE Iridix WDR Look-up-table
          4. 6.7.3.5.4 GLBCE Embedded Memory
          5. 6.7.3.5.5 GLBCE General Processing
          6. 6.7.3.5.6 GLBCE Continuous Frame Processing
          7. 6.7.3.5.7 GLBCE Single Image Processing
        6. 6.7.3.6 VISS Flexible Color Processing (FCP) Module
          1. 6.7.3.6.1 FCP Overview
            1. 6.7.3.6.1.1 FCP Features Supported
          2. 6.7.3.6.2 FCP Functional Description
          3. 6.7.3.6.3 FCP Submodule Details
            1. 6.7.3.6.3.1 Flexible CFA / Demosaicing
              1. 6.7.3.6.3.1.1 Feature-set
              2. 6.7.3.6.3.1.2 Block Diagram of Flexible CFA
                1. 6.7.3.6.3.1.2.1 Gradient/Threshold Calculation
                2. 6.7.3.6.3.1.2.2 Software Controlled Direction Selection
              3. 6.7.3.6.3.1.3 Example Filter Coefficients - Green Interpolation
                1. 6.7.3.6.3.1.3.1 Example Filter Coefficients - Red/Blue Interpolation
              4. 6.7.3.6.3.1.4 CFA 16-Bit Upgrade
              5. 6.7.3.6.3.1.5 FIR Filter Output Scaling
              6. 6.7.3.6.3.1.6 Decopanding, 24-bit Color Conversion Matrix and Companding Blocks
                1. 6.7.3.6.3.1.6.1 The DcmpdLUT Block
                2. 6.7.3.6.3.1.6.2 The CCM Block
                3. 6.7.3.6.3.1.6.3 The CmpdLUT Block
                4. 6.7.3.6.3.1.6.4 Controls for the Decompanding, CCM, and Companding Blocks
                5. 6.7.3.6.3.1.6.5 Example Use Cases
            2. 6.7.3.6.3.2 Edge Enhancer Module Wrapper (WEE)
              1. 6.7.3.6.3.2.1 Align 12 Block
              2. 6.7.3.6.3.2.2 Align 8 Block
              3. 6.7.3.6.3.2.3 Mux Blocks
              4. 6.7.3.6.3.2.4 SL - Shift Left Block
              5. 6.7.3.6.3.2.5 EE - Edge Enhancer Block
              6. 6.7.3.6.3.2.6 SR - Shift Right Block
              7. 6.7.3.6.3.2.7 Edge Enhancer Module Wrapper (WEE) Registers
            3. 6.7.3.6.3.3 Flexible Color Conversion (CC)
              1. 6.7.3.6.3.3.1 Interface Mux
              2. 6.7.3.6.3.3.2 Color Conversion (CCM-1)
              3. 6.7.3.6.3.3.3 RGB to HSX Conversion
                1. 6.7.3.6.3.3.3.1 Weighted Average Block
                2. 6.7.3.6.3.3.3.2 Saturation Block
                3. 6.7.3.6.3.3.3.3 Division Block
                4. 6.7.3.6.3.3.3.4 LUT Based 12 to 8 Downsampling
              4. 6.7.3.6.3.3.4 Histogram
              5. 6.7.3.6.3.3.5 Contrast Stretch / Gamma
              6. 6.7.3.6.3.3.6 RGB-YUV Conversion
            4. 6.7.3.6.3.4 444-422/420 Chroma Down-sampler
            5. 6.7.3.6.3.5 Blanking and Latency
          4. 6.7.3.6.4 FCP Clocking
          5. 6.7.3.6.5 FCP Interrupts
          6. 6.7.3.6.6 FCP Programmer’s Guide
            1. 6.7.3.6.6.1 HWA Core Programming Details
            2. 6.7.3.6.6.2 HWA HTS Programming Details
            3. 6.7.3.6.6.3 HWA Data Transfer Programming Details
            4. 6.7.3.6.6.4 Initialization Sequence
            5. 6.7.3.6.6.5 Real-time Operating Requirements
            6. 6.7.3.6.6.6 Power Up/Down Sequence
        7. 6.7.3.7 VISS Edge Enhancer (EE)
          1. 6.7.3.7.1 Edge Enhancer Introduction
            1. 6.7.3.7.1.1 Edge Enhancer Filter
            2. 6.7.3.7.1.2 Edge Sharpener Filter
            3. 6.7.3.7.1.3 Merge Block
          2. 6.7.3.7.2 Edge Enhancer Programming Model
      4. 6.7.4 VPAC Lens Distortion Correction (LDC) Module
        1. 6.7.4.1 LDC Overview
          1. 6.7.4.1.1 LDC Features
        2. 6.7.4.2 LDC Functional Description
          1. 6.7.4.2.1  LDC Integration in VPAC
          2. 6.7.4.2.2  LDC Block Diagram
          3. 6.7.4.2.3  LDC Clocks
          4. 6.7.4.2.4  LDC Interrupts
            1. 6.7.4.2.4.1 LDC Interrupt Events Description
              1. 6.7.4.2.4.1.1 PIX_IBLK_OUTOFBOUND
              2. 6.7.4.2.4.1.2 MESH_IBLK_OUTOFBOUND
              3. 6.7.4.2.4.1.3 IFR_OUTOFBOUND
              4. 6.7.4.2.4.1.4 INT_SZOVF
              5. 6.7.4.2.4.1.5 VPAC_LDC_FR_DONE_EVT
              6. 6.7.4.2.4.1.6 VPAC_LDC_SL2_WR_ERR
              7. 6.7.4.2.4.1.7 PIX_IBLK_MEMOVF
              8. 6.7.4.2.4.1.8 MESH_IBLK_MEMOVF
              9. 6.7.4.2.4.1.9 VPAC_LDC_VBUSM_RD_ERR
          5. 6.7.4.2.5  LDC Affine Transform
          6. 6.7.4.2.6  LDC Perspective Transformation
          7. 6.7.4.2.7  LDC Lens Distortion Back Mapping
            1. 6.7.4.2.7.1 LDC Mesh Table Storage Format
          8. 6.7.4.2.8  LDC Pixel Interpolation
          9. 6.7.4.2.9  LDC Buffer Management
            1. 6.7.4.2.9.1 LDC Buffer Management
          10. 6.7.4.2.10 LDC Multi Region with Variable Block size
            1. 6.7.4.2.10.1 LDC Region Skip Feature
            2. 6.7.4.2.10.2 LDC Support for sub-set of 3x3 regions
            3. 6.7.4.2.10.3 LDC Limitations of Multi Region Scheme
            4. 6.7.4.2.10.4 LDC Multi Region Block Constrains
          11. 6.7.4.2.11 LDC Multi-pass Frame processing
          12. 6.7.4.2.12 LDC Input/Output Data Formats
          13. 6.7.4.2.13 LDC YUV422 to YUV420 Conversion
          14. 6.7.4.2.14 Independent Channel Control
          15. 6.7.4.2.15 LDC SL2 Interface (LSE)
            1. 6.7.4.2.15.1 LDC PSA (Parallel Signature Analysis)
          16. 6.7.4.2.16 LDC LUT Mapped Dual Output
          17. 6.7.4.2.17 LDC Band Width Controller
          18. 6.7.4.2.18 LDC Input Block Fetch Limit
          19. 6.7.4.2.19 LDC HTS Interface
          20. 6.7.4.2.20 LDC VBUSM Read Interface
          21. 6.7.4.2.21 Partial Input Frame Storage
          22. 6.7.4.2.22 Hybrid Addressing
        3. 6.7.4.3 LDC Programmers Guide
          1. 6.7.4.3.1 LDC Programming Geometric Distortion Mode
          2. 6.7.4.3.2 LDC Programming Rotational Video Stabilization (Affine Transformation)
          3. 6.7.4.3.3 LDC Programming Perspective Transformation
          4. 6.7.4.3.4 LDC Programming LSE
          5. 6.7.4.3.5 LDC Programming Restrictions and Special Cases
      5. 6.7.5 VPAC Multi-Scaler (MSC)
        1. 6.7.5.1 MSC Overview
          1. 6.7.5.1.1 MSC Features
        2. 6.7.5.2 MSC Functional Description
          1. 6.7.5.2.1 MSC Functional Overview
          2. 6.7.5.2.2 Resizer Algorithm Details
            1. 6.7.5.2.2.1 Multiple Scales Generations
            2. 6.7.5.2.2.2 Polyphase Filter
              1. 6.7.5.2.2.2.1 Interpolation/Resampling
              2. 6.7.5.2.2.2.2 Phase Calculation and Re-sampler
              3. 6.7.5.2.2.2.3 Shared Coefficient Buffers
              4. 6.7.5.2.2.2.4 Border Pixel Padding
            3. 6.7.5.2.2.3 ROI Handling
          3. 6.7.5.2.3 MSC Data Formats Supported
        3. 6.7.5.3 MSC Interrupt Conditions
          1. 6.7.5.3.1 CPU Interrupts
          2. 6.7.5.3.2 Interrupt Event Description
            1. 6.7.5.3.2.1 VPAC_MSC_LSE_FR_DONE_EVT_0/1 Events
            2. 6.7.5.3.2.2 VPAC_MSC_LSE_SL2_RD_ERR Interrupt Event
            3. 6.7.5.3.2.3 VPAC_MSC_LSE_SL2_WR_ERR Interrupt Event
        4. 6.7.5.4 MSC Submodule Details
          1. 6.7.5.4.1 MSC Configuration Interface (MSC_CFG)
          2. 6.7.5.4.2 MSC Load Store Engine (MSC_LSE)
            1. 6.7.5.4.2.1 MSC_LSE Overview
              1. 6.7.5.4.2.1.1 MSC_LSE Features
            2. 6.7.5.4.2.2 MSC_LSE Internal Data Loopback Channel
            3. 6.7.5.4.2.3 MSC_LSE PSA Support
            4. 6.7.5.4.2.4 MSC_LSE Feature Detailed Description
          3. 6.7.5.4.3 MSC_CORE (HWA Core)
            1. 6.7.5.4.3.1 MSC_CORE Overview
            2. 6.7.5.4.3.2 Polyphase Filter of Vertical/Horizontal Resizers
              1. 6.7.5.4.3.2.1 Filter Data Path Logic
              2. 6.7.5.4.3.2.2 Filter Phase Calculation
              3. 6.7.5.4.3.2.3 Filter Parameters
              4. 6.7.5.4.3.2.4 Single-Phase Filter Parameters
              5. 6.7.5.4.3.2.5 Interleaved Mode Handling
              6. 6.7.5.4.3.2.6 Input Skip Line Support
            3. 6.7.5.4.3.3 Scaler Filter Thread Mapping
            4. 6.7.5.4.3.4 Filter Coefficients
              1. 6.7.5.4.3.4.1 Filter Coefficient Selection Algorithm
              2. 6.7.5.4.3.4.2 Filter Coefficient Parameter Configuration
              3. 6.7.5.4.3.4.3 3/4/5-Tap Filter Configuration
            5. 6.7.5.4.3.5 Input/Output ROI Trimmers
        5. 6.7.5.5 MSC Performance
        6. 6.7.5.6 MSC Clocking
        7. 6.7.5.7 MSC Reset
        8. 6.7.5.8 MSC Programmer’s Guide
          1. 6.7.5.8.1 Programming Model
            1. 6.7.5.8.1.1 MSC Programming Guidelines
            2. 6.7.5.8.1.2 MSC_Core Programming Details
            3. 6.7.5.8.1.3 MSC_LSE Programming Details
              1. 6.7.5.8.1.3.1 Input Thread Configuration:
              2. 6.7.5.8.1.3.2 Output Channel Configuration
            4. 6.7.5.8.1.4 MSC HTS Programming Details
            5. 6.7.5.8.1.5 MSC Data Transfer Programming Details
            6. 6.7.5.8.1.6 LSE Interrupt Programming
          2. 6.7.5.8.2 Initialization Sequence
          3. 6.7.5.8.3 Real-Time Operating Requirements
          4. 6.7.5.8.4 Power Up/Down Sequence
      6. 6.7.6 VPAC Noise Filter (NF)
        1. 6.7.6.1 NF Overview
          1. 6.7.6.1.1 NF Supported Features
          2. 6.7.6.1.2 NF Not Supported Features
        2. 6.7.6.2 NF Functional Description
          1. 6.7.6.2.1 Functional Operation
            1. 6.7.6.2.1.1 Overview
            2. 6.7.6.2.1.2 NF Integration In VPAC
            3. 6.7.6.2.1.3 Algorithm Details
            4. 6.7.6.2.1.4 Data Format Support In VPAC
        3. 6.7.6.3 NF Interrupts
          1. 6.7.6.3.1 CPU Interrupts
          2. 6.7.6.3.2 Interrupt Event Description
            1. 6.7.6.3.2.1 NF_FRAME_DONE Event
            2. 6.7.6.3.2.2 NF_SL2_READ_ERROR Event
            3. 6.7.6.3.2.3 NF_SL2_WRITE_ERROR Event
        4. 6.7.6.4 NF Submodule Details
          1. 6.7.6.4.1 NF_CFG
            1. 6.7.6.4.1.1 VBUSP Configuration Interface
            2. 6.7.6.4.1.2 Configuration Register Address Map
          2. 6.7.6.4.2 NF_LSE
            1. 6.7.6.4.2.1 NF_LSE Overview
            2. 6.7.6.4.2.2 NF_LSE Feature Detailed Description
          3. 6.7.6.4.3 HTS Interface And Integration
            1. 6.7.6.4.3.1 Hardware Thread Scheduler (HTS)
            2. 6.7.6.4.3.2 Synchronization With HTS
          4. 6.7.6.4.4 Noise Filter Core Block Diagram
            1. 6.7.6.4.4.1 VP Port (NF_LSE To/From NF_CORE Over VBUSP Interface)
            2. 6.7.6.4.4.2 Space Weight Details
            3. 6.7.6.4.4.3 Weight Calculation Logic
              1. 6.7.6.4.4.3.1 Combined LUT For Space And Range Weights
            4. 6.7.6.4.4.4 Reciprocal Calculation Logic
            5. 6.7.6.4.4.5 Border Handling
              1. 6.7.6.4.4.5.1 Border Handling (Simple)
          5. 6.7.6.4.5 Usage As Generic 2D Filter Engine
          6. 6.7.6.4.6 Adaptive Bilateral Weight Support
          7. 6.7.6.4.7 Chroma Handling (Interleaved Mode)
        5. 6.7.6.5 NF Integration Details
          1. 6.7.6.5.1 Performance Requirements
          2. 6.7.6.5.2 Slave VBUSP Interface Clock
          3. 6.7.6.5.3 Clocking
        6. 6.7.6.6 NF Programmer’s Guide
          1. 6.7.6.6.1 Programming Model
            1. 6.7.6.6.1.1 HWA Core Programming Details
            2. 6.7.6.6.1.2 NF SL2 Wrapper Interface Programming Details
            3. 6.7.6.6.1.3 HWA HTS Programming Details
            4. 6.7.6.6.1.4 HWA Data Transfer Programming Details
          2. 6.7.6.6.2 Initialization Sequence
          3. 6.7.6.6.3 Real-Time Operating Requirements
          4. 6.7.6.6.4 Power Up/Down Sequence
          5. 6.7.6.6.5 Clock Stop
    8. 6.8 Depth and Motion Perception Accelerator (DMPAC)
      1. 6.8.1 DMPAC Overview
        1. 6.8.1.1 DMPAC Features
  9. 7 Interprocessor Communication
    1. 7.1 Mailbox
      1. 7.1.1 Mailbox Overview
        1. 7.1.1.1 Mailbox Features
        2. 7.1.1.2 Mailbox Parameters
      2. 7.1.2 Mailbox Integration
        1. 7.1.2.1 System Mailbox Integration
      3. 7.1.3 Mailbox Functional Description
        1. 7.1.3.1 Mailbox Block Diagram
        2. 7.1.3.2 Mailbox Software Reset
        3. 7.1.3.3 Mailbox Power Management
        4. 7.1.3.4 Mailbox Interrupt Requests
        5. 7.1.3.5 Mailbox Assignment
          1. 7.1.3.5.1 Description
        6. 7.1.3.6 Sending and Receiving Messages
          1. 7.1.3.6.1 Description
        7. 7.1.3.7 Example of Communication
      4. 7.1.4 Mailbox Programming Guide
        1. 7.1.4.1 Mailbox Low-level Programming Models
          1. 7.1.4.1.1 Global Initialization
            1. 7.1.4.1.1.1 Surrounding Modules Global Initialization
            2. 7.1.4.1.1.2 Mailbox Global Initialization
              1. 7.1.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
          2. 7.1.4.1.2 Mailbox Operational Modes Configuration
            1. 7.1.4.1.2.1 Mailbox Processing modes
              1. 7.1.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
              2. 7.1.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
              3. 7.1.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
              4. 7.1.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
          3. 7.1.4.1.3 Mailbox Events Servicing
            1. 7.1.4.1.3.1 Events Servicing in Sending Mode
            2. 7.1.4.1.3.2 Events Servicing in Receiving Mode
    2. 7.2 Spinlock
      1. 7.2.1 Spinlock Overview
      2. 7.2.2 Spinlock Functional Description
        1. 7.2.2.1 Spinlock Software Reset
        2. 7.2.2.2 Spinlock Power Management
        3. 7.2.2.3 About Spinlocks
        4. 7.2.2.4 Spinlock Functional Operation
      3. 7.2.3 Spinlock Programming Guide
        1. 7.2.3.1 Spinlock Low-level Programming Models
          1. 7.2.3.1.1 Basic Spinlock Operations
            1. 7.2.3.1.1.1 Spinlocks Clearing After a System Bug Recovery
            2. 7.2.3.1.1.2 Take and Release Spinlock
  10. 8 Memory Controllers
    1. 8.1 Multicore Shared Memory Controller (MSMC)
      1. 8.1.1 MSMC Overview
        1. 8.1.1.1 MSMC Not Supported Features
      2. 8.1.2 MSMC Functional Description
        1. 8.1.2.1  MSMC Block Diagram
        2. 8.1.2.2  MSMC On-Chip Memory Banking
        3. 8.1.2.3  MSMC Snoop Filter and Data Cache
          1. 8.1.2.3.1 Way Partitioning
          2. 8.1.2.3.2 Cache Size Configuration and Associativity
        4. 8.1.2.4  MSMC Access Protection Checks
        5. 8.1.2.5  MSMC Null Slave
        6. 8.1.2.6  MSMC Resource Arbitration
        7. 8.1.2.7  MSMC Error Detection and Correction
          1. 8.1.2.7.1 On-chip SRAM and Pipeline Data Protection
          2. 8.1.2.7.2 On-chip SRAM L3 Cache Tag and Snoop Filter Protection
          3. 8.1.2.7.3 On-chip SRAM Memory Mapped SRAM Snoop Filter Protection
          4. 8.1.2.7.4 Background Parity Refresh (Scrubbing)
        8. 8.1.2.8  MSMC Interrupts
          1. 8.1.2.8.1 Raw Interrupt Registers
          2. 8.1.2.8.2 Interrupt Enable Registers
          3. 8.1.2.8.3 Triggered and Enabled Interrupts
        9. 8.1.2.9  MSMC Memory Regions
        10. 8.1.2.10 MSMC Hardware Coherence
          1. 8.1.2.10.1 Snoop Filter Broadcast Mode
        11. 8.1.2.11 MSMC Quality-of-Service
        12. 8.1.2.12 MSMC Memory Regions Protection
        13. 8.1.2.13 MSMC Cache Tag View
        14. 8.1.2.14 MSMC R50+ Features
          1. 8.1.2.14.1 Way Group Partitioning
            1. 8.1.2.14.1.1 MMRs Related to Way Group Partitioning Feature
              1. 8.1.2.14.1.1.1 RT_WAY_SELECT [Address = 0x8000]
              2. 8.1.2.14.1.1.2 NRT_WAY_SELECT [Address = 0x8008]
          2. 8.1.2.14.2 Write Back Invalidate
            1. 8.1.2.14.2.1 MMR Related to Snoop Filter Invalidate Feature
              1. 8.1.2.14.2.1.1 WBINV_CTRL [Address = 0x4000]
          3. 8.1.2.14.3 FFI Support
            1. 8.1.2.14.3.1 FFI Event Sequence
          4. 8.1.2.14.4 Broadcast Mode
          5. 8.1.2.14.5 DRU and SDMA Access Constraints (Access ARC Removal)
          6. 8.1.2.14.6 EMIF Interleaving
          7. 8.1.2.14.7 QoS Fix/RT Hazarding
    2. 8.2 DDR Subsystem (DDRSS)
      1. 8.2.1 DDRSS Overview
      2. 8.2.2 DDRSS Environment
      3. 8.2.3 DDRSS Functional Description
        1. 8.2.3.1 DDRSS MSMC2DDR Bridge
          1. 8.2.3.1.1 VBUSM.C Threads
          2. 8.2.3.1.2 Class of Service (CoS)
          3. 8.2.3.1.3 AXI Write Data All-Strobes
          4. 8.2.3.1.4 Inline ECC for SDRAM Data
            1. 8.2.3.1.4.1 ECC Cache
            2. 8.2.3.1.4.2 ECC Statistics
          5. 8.2.3.1.5 Opcode Checking
          6. 8.2.3.1.6 Address Alias Prevention
          7. 8.2.3.1.7 Data Error Detection and Correction
          8. 8.2.3.1.8 AXI Bus Timeout
        2. 8.2.3.2 DDRSS Interrupts
        3. 8.2.3.3 DDRSS Memory Regions
        4. 8.2.3.4 DDRSS ECC Support
        5. 8.2.3.5 DDRSS Dynamic Frequency Change Interface
        6. 8.2.3.6 DDR Controller Functional Description
          1. 8.2.3.6.1  DDR PHY Interface (DFI)
          2. 8.2.3.6.2  Command Queue
            1. 8.2.3.6.2.1 Placement Logic
            2. 8.2.3.6.2.2 Command Selection Logic
          3. 8.2.3.6.3  Low Power Control
          4. 8.2.3.6.4  Transaction Processing
          5. 8.2.3.6.5  BIST Engine
          6. 8.2.3.6.6  ECC Engine
          7. 8.2.3.6.7  Address Mapping
          8. 8.2.3.6.8  Paging Policy
          9. 8.2.3.6.9  DDR Controller Initialization
          10. 8.2.3.6.10 Programming LPDDR4 Memories
            1. 8.2.3.6.10.1 Frequency Set Point (FSP)
              1. 8.2.3.6.10.1.1 FSP Mode Register Programming During Initialization
              2. 8.2.3.6.10.1.2 FSP Mode Register Programming During Normal Operation
              3. 8.2.3.6.10.1.3 FSP Mode Register Programming During Dynamic Frequency Scaling
            2. 8.2.3.6.10.2 Data Bus Inversion (DBI)
            3. 8.2.3.6.10.3 On-Die Termination
              1. 8.2.3.6.10.3.1 LPDDR4 DQ ODT
              2. 8.2.3.6.10.3.2 LPDDR4 CA ODT
            4. 8.2.3.6.10.4 Byte Lane Swapping
            5. 8.2.3.6.10.5 DQS Interval Oscillator
              1. 8.2.3.6.10.5.1 Oscillator State Machine
            6. 8.2.3.6.10.6 Per-Bank Refresh (PBR)
              1. 8.2.3.6.10.6.1 Normal Operation
              2. 8.2.3.6.10.6.2 Continuous Refresh Request Mode
        7. 8.2.3.7 DDR PHY Functional Description
          1. 8.2.3.7.1  Data Slice
          2. 8.2.3.7.2  Address Slice
            1. 8.2.3.7.2.1 Address Swapping
          3. 8.2.3.7.3  Address/Control Slice
          4. 8.2.3.7.4  Clock Slice
          5. 8.2.3.7.5  DDR PHY Initialization
          6. 8.2.3.7.6  DDR PHY Dynamic Frequency Scaling (DFS)
          7. 8.2.3.7.7  Chip Select and Frequency Based Register Settings
          8. 8.2.3.7.8  Low-Power Modes
          9. 8.2.3.7.9  Training Support
            1. 8.2.3.7.9.1 Write Leveling
            2. 8.2.3.7.9.2 Read Gate Training
            3. 8.2.3.7.9.3 Read Data Eye Training
            4. 8.2.3.7.9.4 Write DQ Training
            5. 8.2.3.7.9.5 CA Training
            6. 8.2.3.7.9.6 CS Training
          10. 8.2.3.7.10 Data Bus Inversion (DBI)
          11. 8.2.3.7.11 I/O Pad Calibration
          12. 8.2.3.7.12 DQS Error
        8. 8.2.3.8 PI Functional Description
          1. 8.2.3.8.1 PI Initialization
      4. 8.2.4 DDRSS Registers
    3. 8.3 Peripheral Virtualization Unit (PVU)
      1. 8.3.1 PVU Overview
        1. 8.3.1.1 PVU Features
        2. 8.3.1.2 PVU Parameters
      2. 8.3.2 PVU Functional Description
        1. 8.3.2.1  Functional Operation Overview
        2. 8.3.2.2  PVU Channels
        3. 8.3.2.3  TLB
        4. 8.3.2.4  TLB Entry
        5. 8.3.2.5  TLB Selection
        6. 8.3.2.6  DMA Classes
        7. 8.3.2.7  General virtIDs
        8. 8.3.2.8  TLB Lookup
        9. 8.3.2.9  TLB Miss
        10. 8.3.2.10 Multiple Matching Entries
        11. 8.3.2.11 TLB Disable
        12. 8.3.2.12 TLB Chaining
        13. 8.3.2.13 TLB Permissions
        14. 8.3.2.14 Translation
        15. 8.3.2.15 Memory Attributes
        16. 8.3.2.16 Faulted Transactions
        17. 8.3.2.17 Non-Virtual Transactions
        18. 8.3.2.18 Allowed virtIDs
        19. 8.3.2.19 Software Control
        20. 8.3.2.20 Fault Logging
        21. 8.3.2.21 Alignment Restrictions
    4. 8.4 Region-based Address Translation (RAT) Module
      1. 8.4.1 RAT Functional Description
        1. 8.4.1.1 RAT Availability
        2. 8.4.1.2 RAT Operation
        3. 8.4.1.3 RAT Error Logging
  11. 9 Interrupts
    1. 9.1 Interrupt Architecture
    2. 9.2 Interrupt Controllers
      1. 9.2.1 Generic Interrupt Controller (GIC)
        1. 9.2.1.1 GIC Overview
          1. 9.2.1.1.1 GIC Features
          2. 9.2.1.1.2 GIC Not Supported Features
        2. 9.2.1.2 GIC Functional Description
          1. 9.2.1.2.1 Arm GIC-500
          2. 9.2.1.2.2 GIC Interrupt Types
          3. 9.2.1.2.3 GIC Interfaces
          4. 9.2.1.2.4 GIC Interrupt Outputs
          5. 9.2.1.2.5 GIC ECC Support
          6. 9.2.1.2.6 GIC AXI2VBUSM and VBUSM2AXI Bridges
      2. 9.2.2 Cluster Level Event Controller (CLEC)
        1. 9.2.2.1 CLEC Overview
        2. 9.2.2.2 CLEC Functional Description
          1. 9.2.2.2.1 CLEC Interrupt Event Routing
          2. 9.2.2.2.2 CLEC Virtualization, Isolation and Access Control
          3. 9.2.2.2.3 CLEC Memory Protection
          4. 9.2.2.2.4 CLEC ECC Support
          5. 9.2.2.2.5 CLEC Intra-Core Communication
          6. 9.2.2.2.6 CLEC Event Maps
            1. 9.2.2.2.6.1 CLEC ESM Event Routing
      3. 9.2.3 Other Interrupt Controllers
    3. 9.3 Interrupt Routers
      1. 9.3.1 INTRTR Overview
      2. 9.3.2 INTRTR Registers
        1. 9.3.2.1 CMPEVENT_INTRTR Registers
        2. 9.3.2.2 GPIOMUX_INTRTR Registers
        3. 9.3.2.3 MAIN2MCU_LVL_INTRTR Registers
        4. 9.3.2.4 MAIN2MCU_PLS_INTRTR Registers
        5. 9.3.2.5 TIMESYNC_INTRTR Registers
    4. 9.4 Interrupt Sources
      1. 9.4.1  A72SS0_INTERRUPT_MAP
      2. 9.4.2  CMPEVENT_INTRTR0_INTERRUPT_MAP
      3. 9.4.3  COMPUTE_CLUSTER0_C71SS0_0_INTERRUPT_MAP
      4. 9.4.4  COMPUTE_CLUSTER0_C71SS1_0_INTERRUPT_MAP
      5. 9.4.5  COMPUTE_CLUSTER0_CLEC_INTERRUPT_MAP
      6. 9.4.6  COMPUTE_CLUSTER0_CORE_CORE_INTERRUPT_MAP
      7. 9.4.7  COMPUTE_CLUSTER0_DRU_INTERRUPT_MAP
      8. 9.4.8  COMPUTE_CLUSTER0_GIC500SS_INTERRUPT_MAP
      9. 9.4.9  CPSW1_INTERRUPT_MAP
      10. 9.4.10 DMPAC0_INTD_0_INTERRUPT_MAP
      11. 9.4.11 ESM0_INTERRUPT_MAP
      12. 9.4.12 GLUELOGIC_A72_IPC_INTR_GLUE_INTERRUPT_MAP
      13. 9.4.13 GLUELOGIC_DBG_CBASS_INTR_OR_GLUE_INTERRUPT_MAP
      14. 9.4.14 GLUELOGIC_FW_CBASS_INTR_OR_GLUE_INTERRUPT_MAP
      15. 9.4.15 GLUELOGIC_GPU_GPIO_INT_GLUE_INTERRUPT_MAP
      16. 9.4.16 GLUELOGIC_MAIN_CBASS_INTR_OR_GLUE_INTERRUPT_MAP
      17. 9.4.17 GLUELOGIC_NONFW_CBASS_INTR_OR_GLUE_INTERRUPT_MAP
      18. 9.4.18 GPIOMUX_INTRTR0_INTERRUPT_MAP
      19. 9.4.19 MAIN_GPIO0_VIRT_INTERRUPT_MAP
      20. 9.4.20 MAIN2MCU_LVL_INTRTR0_INTERRUPT_MAP
      21. 9.4.21 MAIN2MCU_PLS_INTRTR0_INTERRUPT_MAP
      22. 9.4.22 MCU_ADC12FCC0_INTERRUPT_MAP
      23. 9.4.23 MCU_ADC12FCC1_INTERRUPT_MAP
      24. 9.4.24 MCU_CPSW0_INTERRUPT_MAP
      25. 9.4.25 MCU_ESM0_INTERRUPT_MAP
      26. 9.4.26 MCU_NAVSS0_INTR_ROUTER_0_INTERRUPT_MAP
      27. 9.4.27 MCU_NAVSS0_UDMASS_INTA_0_INTERRUPT_MAP
      28. 9.4.28 MCU_PDMA0_INTERRUPT_MAP
      29. 9.4.29 MCU_PDMA1_INTERRUPT_MAP
      30. 9.4.30 MCU_PDMA3_INTERRUPT_MAP
      31. 9.4.31 MCU_PDMA2_INTERRUPT_MAP
      32. 9.4.32 MCU_R5FSS0_CORE0_INTERRUPT_MAP
      33. 9.4.33 MCU_R5FSS0_CORE1_INTERRUPT_MAP
      34. 9.4.34 NAVSS0_INTR_0_INTERRUPT_MAP
      35. 9.4.35 NAVSS0_INTERRUPT_MAP
      36. 9.4.36 NAVSS0_UDMASS_INTA_0_INTERRUPT_MAP
      37. 9.4.37 PCIE1_INTERRUPT_MAP
      38. 9.4.38 PINFUNCTION_SYNC0_OUTOUT_INTERRUPT_MAP
      39. 9.4.39 PINFUNCTION_SYNC1_OUTOUT_INTERRUPT_MAP
      40. 9.4.40 PINFUNCTION_SYNC2_OUTOUT_INTERRUPT_MAP
      41. 9.4.41 PINFUNCTION_SYNC3_OUTOUT_INTERRUPT_MAP
      42. 9.4.42 PDMA0_INTERRUPT_MAP
      43. 9.4.43 PDMA1_INTERRUPT_MAP
      44. 9.4.44 PDMA2_INTERRUPT_MAP
      45. 9.4.45 PDMA3_INTERRUPT_MAP
      46. 9.4.46 PDMA4_INTERRUPT_MAP
      47. 9.4.47 PDMA5_INTERRUPT_MAP
      48. 9.4.48 PDMA6_INTERRUPT_MAP
      49. 9.4.49 PDMA7_INTERRUPT_MAP
      50. 9.4.50 PDMA8_INTERRUPT_MAP
      51. 9.4.51 R5FSS0_CORE0_INTERRUPT_MAP
      52. 9.4.52 R5FSS0_CORE1_INTERRUPT_MAP
      53. 9.4.53 R5FSS1_CORE0_INTERRUPT_MAP
      54. 9.4.54 R5FSS1_CORE1_INTERRUPT_MAP
      55. 9.4.55 TIMESYNC_INTRTR0_INTERRUPT_MAP
      56. 9.4.56 VUSR_DUAL0_INTERRUPT_MAP
      57. 9.4.57 WKUP_ESM0_INTERRUPT_MAP
      58. 9.4.58 WKUP_GPIO_VIRT_INTERRUPT_MAP
      59. 9.4.59 WKUP_GPIOMUX_INTRTR0_INTERRUPT_MAP
      60. 9.4.60 WKUP_HSM0_INTERRUPT_MAP
      61. 9.4.61 WKUP_SMS0_COMMON_0_INTERRUPT_MAP
      62. 9.4.62 WKUP_TIFS0_INTERRUPT_MAP
  12. 10Data Movement Architecture (DMA)
    1. 10.1 DMA Architecture
      1. 10.1.1 Overview
        1. 10.1.1.1  Navigator Subsystem
        2. 10.1.1.2  Ring Accelerator (RA)
        3. 10.1.1.3  Proxy
        4. 10.1.1.4  Secure Proxy
        5. 10.1.1.5  Interrupt Aggregator (INTA)
        6. 10.1.1.6  Interrupt Router (IR)
        7. 10.1.1.7  Unified DMA – Third Party Channel Controller (UDMA-C)
        8. 10.1.1.8  Unified Transfer Controller (UTC)
        9. 10.1.1.9  Data Routing Unit (DRU)
        10. 10.1.1.10 Unified DMA – Peripheral Root Complex (UDMA-P)
        11. 10.1.1.11 Peripheral DMA (PDMA)
        12. 10.1.1.12 Embedded DMA
        13. 10.1.1.13 Definition of Terms
      2. 10.1.2 UDMA Hardware/Software Interface
        1. 10.1.2.1 Data Buffers
        2. 10.1.2.2 Descriptors
          1. 10.1.2.2.1 Host Packet Descriptor
          2. 10.1.2.2.2 Host Buffer Descriptor
          3. 10.1.2.2.3 Monolithic Packet Descriptor
          4. 10.1.2.2.4 Transfer Request Descriptor
        3. 10.1.2.3 Transfer Request Record
          1. 10.1.2.3.1 Overview
          2. 10.1.2.3.2 Addressing Algorithm
            1. 10.1.2.3.2.1 Linear Addressing (Forward)
          3. 10.1.2.3.3 Transfer Request Formats
          4. 10.1.2.3.4 Flags Field Definition
            1. 10.1.2.3.4.1 Type: TR Type Field
            2. 10.1.2.3.4.2 STATIC: Static Field Definition
            3. 10.1.2.3.4.3 EVENT_SIZE: Event Generation Definition
            4. 10.1.2.3.4.4 TRIGGER INFO: TR Triggers
            5. 10.1.2.3.4.5 TRIGGERX_TYPE: Trigger Type
            6. 10.1.2.3.4.6 TRIGGERX: Trigger Selection
            7. 10.1.2.3.4.7 CMD ID: Command ID Field Definition
            8. 10.1.2.3.4.8 Configuration Specific Flags Definition
          5. 10.1.2.3.5 TR Address and Size Attributes
            1. 10.1.2.3.5.1  ICNT0
            2. 10.1.2.3.5.2  ICNT1
            3. 10.1.2.3.5.3  ADDR
            4. 10.1.2.3.5.4  DIM1
            5. 10.1.2.3.5.5  ICNT2
            6. 10.1.2.3.5.6  ICNT3
            7. 10.1.2.3.5.7  DIM2
            8. 10.1.2.3.5.8  DIM3
            9. 10.1.2.3.5.9  DDIM1
            10. 10.1.2.3.5.10 DADDR
            11. 10.1.2.3.5.11 DDIM2
            12. 10.1.2.3.5.12 DDIM3
            13. 10.1.2.3.5.13 DICNT0
            14. 10.1.2.3.5.14 DICNT1
            15. 10.1.2.3.5.15 DICNT2
            16. 10.1.2.3.5.16 DICNT3
          6. 10.1.2.3.6 FMTFLAGS
            1. 10.1.2.3.6.1 AMODE: Addressing Mode Definition
              1. 10.1.2.3.6.1.1 Linear Addressing
              2. 10.1.2.3.6.1.2 Circular Addressing
            2. 10.1.2.3.6.2 DIR: Addressing Mode Direction Definition
            3. 10.1.2.3.6.3 ELTYPE: Element Type Definition
            4. 10.1.2.3.6.4 DFMT: Data Formatting Algorithm Definition
            5. 10.1.2.3.6.5 SECTR: Secondary Transfer Request Definition
              1. 10.1.2.3.6.5.1 Secondary TR Formats
              2. 10.1.2.3.6.5.2 Secondary TR FLAGS
                1. 10.1.2.3.6.5.2.1 SEC_TR_TYPE: Secondary TR Type Field
                2. 10.1.2.3.6.5.2.2 Multiple Buffer Interleave
            6. 10.1.2.3.6.6 AMODE SPECIFIC: Addressing Mode Field
              1. 10.1.2.3.6.6.1 Circular Address Mode Specific Flags
                1. 10.1.2.3.6.6.1.1 CBK0 and CBK1: Circular Block Size Selection
                2. 10.1.2.3.6.6.1.2 Amx: Addressing Mode Selection
            7. 10.1.2.3.6.7 Cache Flags
        4. 10.1.2.4 Transfer Response Record
          1. 10.1.2.4.1 STATUS Field Definition
            1. 10.1.2.4.1.1 STATUS_TYPE Definition
              1. 10.1.2.4.1.1.1 Transfer Error
              2. 10.1.2.4.1.1.2 Aborted Error
              3. 10.1.2.4.1.1.3 Submission Error
              4. 10.1.2.4.1.1.4 Unsupported Feature
              5. 10.1.2.4.1.1.5 Transfer Exception
              6. 10.1.2.4.1.1.6 Teardown Flush
        5. 10.1.2.5 Queues
          1. 10.1.2.5.1 Queue Types
            1. 10.1.2.5.1.1 Transmit Queues (Pass By Reference)
            2. 10.1.2.5.1.2 Transmit Queues (Pass By Value)
            3. 10.1.2.5.1.3 Transmit Completion Queues (Pass By Reference)
            4. 10.1.2.5.1.4 Transmit Completion Queues (Pass By Value)
            5. 10.1.2.5.1.5 Receive Queues
            6. 10.1.2.5.1.6 Free Descriptor Queues
            7. 10.1.2.5.1.7 Free Descriptor/Buffer Queues
          2. 10.1.2.5.2 Ring Accelerator Queues Implementation
      3. 10.1.3 Operational Description
        1. 10.1.3.1  Resource Allocation
        2. 10.1.3.2  Ring Accelerator Operation
          1. 10.1.3.2.1 Queue Initialization
          2. 10.1.3.2.2 Queuing packets (Exposed Ring Mode)
          3. 10.1.3.2.3 De-queuing packets (Exposed Ring Mode)
          4. 10.1.3.2.4 Queuing packets (Queue Mode)
          5. 10.1.3.2.5 De-queuing packets (Queue Mode)
        3. 10.1.3.3  UDMA Internal Transmit Channel Setup (All Packet Types)
        4. 10.1.3.4  UDMA Internal Transmit Channel Teardown (All Packet Types)
        5. 10.1.3.5  UDMA-P Transmit Channel Pause
        6. 10.1.3.6  UDMA-P Transmit Operation (Host Packet Type)
        7. 10.1.3.7  UDMA-P Transmit Operation (Monolithic Packet)
        8. 10.1.3.8  UDMA Transmit Operation (TR Packet)
        9. 10.1.3.9  UDMA Transmit Operation (Direct TR)
        10. 10.1.3.10 UDMA Transmit Error/Exception Handling
          1. 10.1.3.10.1 Null Icnt0 Error
          2. 10.1.3.10.2 Unsupported TR Type
          3. 10.1.3.10.3 Bus Errors
        11. 10.1.3.11 UDMA Receive Channel Setup (All Packet Types)
        12. 10.1.3.12 UDMA Receive Channel Teardown
        13. 10.1.3.13 UDMA-P Receive Channel Pause
        14. 10.1.3.14 UDMA-P Receive Free Descriptor/Buffer Queue Setup (Host Packets)
        15. 10.1.3.15 UDMA-P Receive FlowID Firewall Operation
        16. 10.1.3.16 UDMA-P Receive Operation (Host Packet)
        17. 10.1.3.17 UDMA-P Receive Operation (Monolithic Packet)
        18. 10.1.3.18 UDMA Receive Operation (TR Packet)
        19. 10.1.3.19 UDMA Receive Operation (Direct TR)
        20. 10.1.3.20 UDMA Receive Error/Exception Handling
          1. 10.1.3.20.1 Error Conditions
            1. 10.1.3.20.1.1 Bus Errors
            2. 10.1.3.20.1.2 Null Icnt0 Error
            3. 10.1.3.20.1.3 Unsupported TR Type
          2. 10.1.3.20.2 Exception Conditions Exception Conditions
            1. 10.1.3.20.2.1 Descriptor Starvation
            2. 10.1.3.20.2.2 Protocol Errors
            3. 10.1.3.20.2.3 Dropped Packets
            4. 10.1.3.20.2.4 Reception of EOL Delimiter
            5. 10.1.3.20.2.5 EOP Asserted Prematurely (Short Packet)
            6. 10.1.3.20.2.6 EOP Asserted Late (Long Packets)
        21. 10.1.3.21 UTC Operation
        22. 10.1.3.22 UTC Receive Error/Exception Handling
          1. 10.1.3.22.1 Error Handling
            1. 10.1.3.22.1.1 Null Icnt0 Error
            2. 10.1.3.22.1.2 Unsupported TR Type
          2. 10.1.3.22.2 Exception Conditions
            1. 10.1.3.22.2.1 Reception of EOL Delimiter
            2. 10.1.3.22.2.2 EOP Asserted Prematurely (Short Packet)
            3. 10.1.3.22.2.3 EOP Asserted Late (Long Packets)
    2. 10.2 Navigator Subsystem (NAVSS)
      1. 10.2.1 Main Navigator Subsystem (NAVSS)
        1. 10.2.1.1 NAVSS Overview
        2. 10.2.1.2 NAVSS Functional Description
        3. 10.2.1.3 NAVSS Interrupt Configuration
          1. 10.2.1.3.1 NAVSS Event and Interrupt Flow
            1. 10.2.1.3.1.1 NAVSS Interrupts Description
            2. 10.2.1.3.1.2 Application Example
      2. 10.2.2 MCU Navigator Subsystem (MCU NAVSS)
        1. 10.2.2.1 MCU NAVSS Overview
        2. 10.2.2.2 MCU NAVSS Functional Description
      3. 10.2.3 Unified DMA Controller (UDMA)
        1. 10.2.3.1 UDMA Overview
          1. 10.2.3.1.1 UDMA Features
          2. 10.2.3.1.2 UDMA Parameters
        2. 10.2.3.2 UDMA Functional Description
          1. 10.2.3.2.1 Block Diagram
          2. 10.2.3.2.2 General Functionality
            1. 10.2.3.2.2.1  Operational States
            2. 10.2.3.2.2.2  Tx Channel Allocation
            3. 10.2.3.2.2.3  Rx Channel Allocation
            4. 10.2.3.2.2.4  Tx Teardown
            5. 10.2.3.2.2.5  Rx Teardown
            6. 10.2.3.2.2.6  Tx Clock Stop
            7. 10.2.3.2.2.7  Rx Clock Stop
            8. 10.2.3.2.2.8  Rx Thread Enables
            9. 10.2.3.2.2.9  Events
              1. 10.2.3.2.2.9.1 Local Event Inputs
              2. 10.2.3.2.2.9.2 Inbound Tx PSI-L Events
              3. 10.2.3.2.2.9.3 Outbound Rx PSI-L Events
            10. 10.2.3.2.2.10 Emulation Control
          3. 10.2.3.2.3 Packet Oriented Transmit Operation
            1. 10.2.3.2.3.1 Packet Mode VBUSM Master Interface Command ID Selection
          4. 10.2.3.2.4 Packet Oriented Receive Operation
            1. 10.2.3.2.4.1 Rx Packet Drop
            2. 10.2.3.2.4.2 Rx Starvation and the Starvation Timer
          5. 10.2.3.2.5 Third Party Mode Operation
            1. 10.2.3.2.5.1 Events and Flow Control
              1. 10.2.3.2.5.1.1 Channel Triggering
              2. 10.2.3.2.5.1.2 Internal TR Completion Events
            2. 10.2.3.2.5.2 Transmit Operation
              1. 10.2.3.2.5.2.1 Transfer Request
              2. 10.2.3.2.5.2.2 Transfer Response
              3. 10.2.3.2.5.2.3 Data Transfer
              4. 10.2.3.2.5.2.4 Memory Interface Transactions
              5. 10.2.3.2.5.2.5 Error Handling
            3. 10.2.3.2.5.3 Receive Operation
              1. 10.2.3.2.5.3.1 Transfer Request
              2. 10.2.3.2.5.3.2 Transfer Response
              3. 10.2.3.2.5.3.3 Error Handling
            4. 10.2.3.2.5.4 Data Transfer
              1. 10.2.3.2.5.4.1 Memory Interface Transactions
              2. 10.2.3.2.5.4.2 Rx Packet Drop
      4. 10.2.4 Ring Accelerator (RINGACC)
        1. 10.2.4.1 RINGACC Overview
          1. 10.2.4.1.1 RINGACC Features
          2. 10.2.4.1.2 RINGACC Parameters
        2. 10.2.4.2 RINGACC Functional Description
          1. 10.2.4.2.1 Block Diagram
            1. 10.2.4.2.1.1  Configuration Registers
            2. 10.2.4.2.1.2  Source Command FIFO
            3. 10.2.4.2.1.3  Source Write Data FIFO
            4. 10.2.4.2.1.4  Source Read Data FIFO
            5. 10.2.4.2.1.5  Source Write Status FIFO
            6. 10.2.4.2.1.6  Main State Machine
            7. 10.2.4.2.1.7  Destination Command FIFO
            8. 10.2.4.2.1.8  Destination Write Data FIFO
            9. 10.2.4.2.1.9  Destination Read Data FIFO
            10. 10.2.4.2.1.10 Destination Write Status FIFO
          2. 10.2.4.2.2 RINGACC Functional Operation
            1. 10.2.4.2.2.1 Queue Modes
              1. 10.2.4.2.2.1.1 Ring Mode
              2. 10.2.4.2.2.1.2 Messaging Mode
              3. 10.2.4.2.2.1.3 Credentials Mode
              4. 10.2.4.2.2.1.4 Queue Manager Mode
              5. 10.2.4.2.2.1.5 Peek Support
              6. 10.2.4.2.2.1.6 Index Register Operation
            2. 10.2.4.2.2.2 VBUSM Slave Ring Operations
            3. 10.2.4.2.2.3 VBUSM Master Interface Command ID Selection
            4. 10.2.4.2.2.4 Ring Push Operation (VBUSM Write to Source Interface)
            5. 10.2.4.2.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
            6. 10.2.4.2.2.6 Host Doorbell Access
            7. 10.2.4.2.2.7 Queue Push Operation (VBUSM Write to Source Interface)
            8. 10.2.4.2.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
            9. 10.2.4.2.2.9 Mismatched Element Size Handling
          3. 10.2.4.2.3 Events
          4. 10.2.4.2.4 Bus Error Handling
          5. 10.2.4.2.5 Monitors
            1. 10.2.4.2.5.1 Threshold Monitor
            2. 10.2.4.2.5.2 Watermark Monitor
            3. 10.2.4.2.5.3 Starvation Monitor
            4. 10.2.4.2.5.4 Statistics Monitor
            5. 10.2.4.2.5.5 Overflow
            6. 10.2.4.2.5.6 Ring Update Port
            7. 10.2.4.2.5.7 Tracing
      5. 10.2.5 Proxy
        1. 10.2.5.1 Proxy Overview
          1. 10.2.5.1.1 Proxy Features
          2. 10.2.5.1.2 Proxy Parameters
        2. 10.2.5.2 Proxy Functional Description
          1. 10.2.5.2.1  Targets
            1. 10.2.5.2.1.1 Ring Accelerator
          2. 10.2.5.2.2  Proxy Sizes
          3. 10.2.5.2.3  Proxy Interleaving
          4. 10.2.5.2.4  Proxy Host States
          5. 10.2.5.2.5  Proxy Host Channel Selection
          6. 10.2.5.2.6  Proxy Host Access
            1. 10.2.5.2.6.1 Proxy Host Writes
            2. 10.2.5.2.6.2 Proxy Host Reads
          7. 10.2.5.2.7  Permission Inheritance
          8. 10.2.5.2.8  Buffer Size
          9. 10.2.5.2.9  Error Events
          10. 10.2.5.2.10 Debug Reads
      6. 10.2.6 Secure Proxy
        1. 10.2.6.1 Secure Proxy Overview
          1. 10.2.6.1.1 Secure Proxy Features
          2. 10.2.6.1.2 Secure Proxy Parameters
        2. 10.2.6.2 Secure Proxy Functional Description
          1. 10.2.6.2.1  Targets
            1. 10.2.6.2.1.1 Ring Accelerator
          2. 10.2.6.2.2  Buffers
            1. 10.2.6.2.2.1 Proxy Credits
            2. 10.2.6.2.2.2 Proxy Private Word
            3. 10.2.6.2.2.3 Completion Byte
          3. 10.2.6.2.3  Proxy Thread Sizes
          4. 10.2.6.2.4  Proxy Thread Interleaving
          5. 10.2.6.2.5  Proxy States
          6. 10.2.6.2.6  Proxy Host Access
            1. 10.2.6.2.6.1 Proxy Host Writes
            2. 10.2.6.2.6.2 Proxy Host Reads
            3. 10.2.6.2.6.3 Buffer Accesses
            4. 10.2.6.2.6.4 Target Access
            5. 10.2.6.2.6.5 Error State
          7. 10.2.6.2.7  Permission Inheritance
          8. 10.2.6.2.8  Resource Association
          9. 10.2.6.2.9  Direction
          10. 10.2.6.2.10 Threshold Events
          11. 10.2.6.2.11 Error Events
          12. 10.2.6.2.12 Bus Errors and Credits
          13. 10.2.6.2.13 Debug
      7. 10.2.7 Interrupt Aggregator (INTR_AGGR)
        1. 10.2.7.1 INTR_AGGR Overview
          1. 10.2.7.1.1 INTR_AGGR Features
          2. 10.2.7.1.2 INTR_AGGR Parameters
        2. 10.2.7.2 INTR_AGGR Functional Description
          1. 10.2.7.2.1 Submodule Descriptions
            1. 10.2.7.2.1.1 Status/Mask Registers
            2. 10.2.7.2.1.2 Interrupt Mapping Block
            3. 10.2.7.2.1.3 Global Event Input (GEVI) Counters
            4. 10.2.7.2.1.4 Local Event Input (LEVI) to Global Event Conversion
            5. 10.2.7.2.1.5 Global Event Multicast
          2. 10.2.7.2.2 General Functionality
            1. 10.2.7.2.2.1 Event to Interrupt Bit Steering
            2. 10.2.7.2.2.2 Interrupt Status
            3. 10.2.7.2.2.3 Interrupt Masked Status
            4. 10.2.7.2.2.4 Enabling/Disabling Individual Interrupt Source Bits
            5. 10.2.7.2.2.5 Interrupt Output Generation
            6. 10.2.7.2.2.6 Global Event Counting
            7. 10.2.7.2.2.7 Local Event to Global Event Conversion
            8. 10.2.7.2.2.8 Global Event Multicast
      8. 10.2.8 Packet Streaming Interface Link (PSI-L)
        1. 10.2.8.1 PSI-L Overview
        2. 10.2.8.2 PSI-L Functional Description
          1. 10.2.8.2.1 PSI-L Introduction
          2. 10.2.8.2.2 PSI-L Operation
            1. 10.2.8.2.2.1 Event Transport
            2. 10.2.8.2.2.2 Threads
            3. 10.2.8.2.2.3 Arbitration Protocol
            4. 10.2.8.2.2.4 Thread Configuration
              1. 10.2.8.2.2.4.1 Thread Pairing
                1. 10.2.8.2.2.4.1.1 Configuration Transaction Pairing
              2. 10.2.8.2.2.4.2 Configuration Registers Region
      9. 10.2.9 NAVSS North Bridge (NB)
        1. 10.2.9.1 NB Overview
          1. 10.2.9.1.1 Features Supported
          2. 10.2.9.1.2 NB Parameters
            1. 10.2.9.1.2.1 Compliance to Standards
            2. 10.2.9.1.2.2 Features Not Supported
        2. 10.2.9.2 NB Functional Description
          1. 10.2.9.2.1  VBUSM Slave Interfaces
          2. 10.2.9.2.2  VBUSM Master Interface
          3. 10.2.9.2.3  VBUSM.C Interfaces
            1. 10.2.9.2.3.1 Multi-Threading
            2. 10.2.9.2.3.2 Write Command Crediting
            3. 10.2.9.2.3.3 Early Credit Response
            4. 10.2.9.2.3.4 Priority Escalation
          4. 10.2.9.2.4  Source M2M Bridges
          5. 10.2.9.2.5  Destination M2M Bridge
          6. 10.2.9.2.6  M2C Bridge
          7. 10.2.9.2.7  Memory Attribute Tables
          8. 10.2.9.2.8  Outstanding Read Data Limiter
          9. 10.2.9.2.9  Ordering
          10. 10.2.9.2.10 Quality of Service
          11. 10.2.9.2.11 IDLE Behavior
          12. 10.2.9.2.12 Clock Power Management
    3. 10.3 Peripheral DMA (PDMA)
      1. 10.3.1 PDMA Controller
        1. 10.3.1.1 PDMA Overview
          1. 10.3.1.1.1 PDMA Features
            1. 10.3.1.1.1.1  MCU_PDMA0 (MCU_PDMA_MISC_G0) Features
            2. 10.3.1.1.1.2  MCU_PDMA1 (MCU_PDMA_MISC_G1) Features
            3. 10.3.1.1.1.3  MCU_PDMA2 (MCU_PDMA_MISC_G2) Features
            4. 10.3.1.1.1.4  MCU_PDMA3 (MCU_PDMA_ADC) Features
            5. 10.3.1.1.1.5  PDMA5 (PDMA_MCAN) Features
            6. 10.3.1.1.1.6  PDMA6 (PDMA_MCASP_G0) Features
            7. 10.3.1.1.1.7  PDMA9 (PDMA_SPI_G0) Features
            8. 10.3.1.1.1.8  PDMA10 (PDMA_SPI_G1) Features
            9. 10.3.1.1.1.9  PDMA13 (PDMA_USART_G0) Features
            10. 10.3.1.1.1.10 PDMA14 (PDMA_USART_G1) Features
            11. 10.3.1.1.1.11 PDMA15 (PDMA_USART_G2) Features
        2. 10.3.1.2 PDMA Functional Description
          1. 10.3.1.2.1 PDMA Functional Blocks
            1. 10.3.1.2.1.1 Scheduler
            2. 10.3.1.2.1.2 Tx Per-Channel Buffers (TCP FIFO)
            3. 10.3.1.2.1.3 Tx DMA Unit (Tx Engine)
            4. 10.3.1.2.1.4 Rx Per-Channel Buffers (RCP FIFO)
            5. 10.3.1.2.1.5 Rx DMA Unit (Rx Engine)
          2. 10.3.1.2.2 PDMA General Functionality
            1. 10.3.1.2.2.1 Operational States
            2. 10.3.1.2.2.2 Clock Stop
            3. 10.3.1.2.2.3 Emulation Control
          3. 10.3.1.2.3 PDMA Events and Flow Control
            1. 10.3.1.2.3.1 Channel Types
              1. 10.3.1.2.3.1.1 X-Y FIFO Mode
              2. 10.3.1.2.3.1.2 MCAN Mode
              3. 10.3.1.2.3.1.3 AASRC Mode
            2. 10.3.1.2.3.2 Channel Triggering
            3. 10.3.1.2.3.3 Completion Events
          4. 10.3.1.2.4 PDMA Transmit Operation
            1. 10.3.1.2.4.1 Destination (Tx) Channel Allocation
            2. 10.3.1.2.4.2 Destination (Tx) Channel Out-of-Band Signals
            3. 10.3.1.2.4.3 Destination Channel Initialization
              1. 10.3.1.2.4.3.1 PSI-L Destination Thread Pairing
              2. 10.3.1.2.4.3.2 Static Transfer Request Setup
              3. 10.3.1.2.4.3.3 PSI-L Destination Thread Enables
            4. 10.3.1.2.4.4 Data Transfer
              1. 10.3.1.2.4.4.1 X-Y FIFO Mode Channel
                1. 10.3.1.2.4.4.1.1 X-Y FIFO Burst Mode
              2. 10.3.1.2.4.4.2 MCAN Mode Channel
                1. 10.3.1.2.4.4.2.1 MCAN Burst Mode
              3. 10.3.1.2.4.4.3 AASRC Mode Channel
            5. 10.3.1.2.4.5 Tx Pause
            6. 10.3.1.2.4.6 Tx Teardown
            7. 10.3.1.2.4.7 Tx Channel Reset
            8. 10.3.1.2.4.8 Tx Debug/State Registers
          5. 10.3.1.2.5 PDMA Receive Operation
            1. 10.3.1.2.5.1 Source (Rx) Channel Allocation
            2. 10.3.1.2.5.2 Source Channel Initialization
              1. 10.3.1.2.5.2.1 PSI-L Source Thread Pairing
              2. 10.3.1.2.5.2.2 Static Transfer Request Setup
              3. 10.3.1.2.5.2.3 PSI-L Source Thread Enables
            3. 10.3.1.2.5.3 Data Transfer
              1. 10.3.1.2.5.3.1 X-Y FIFO Mode Channel
              2. 10.3.1.2.5.3.2 MCAN Mode Channel
                1. 10.3.1.2.5.3.2.1 MCAN Burst Mode
              3. 10.3.1.2.5.3.3 AASRC Mode Channel
            4. 10.3.1.2.5.4 Rx Pause
            5. 10.3.1.2.5.5 Rx Teardown
            6. 10.3.1.2.5.6 Rx Channel Reset
            7. 10.3.1.2.5.7 Rx Debug/State Register
          6. 10.3.1.2.6 PDMA ECC Support
      2. 10.3.2 PDMA Sources
        1. 10.3.2.1 MCU Domain PDMA Event Maps
          1. 10.3.2.1.1 MCU_PDMA_MISC_G0 Event Map
          2. 10.3.2.1.2 MCU_PDMA_MISC_G1 Event Map
          3. 10.3.2.1.3 MCU_PDMA_MISC_G2 Event Map
          4. 10.3.2.1.4 MCU_PDMA_ADC Event Map
        2. 10.3.2.2 MAIN Domain PDMA Event Maps
          1. 10.3.2.2.1 PDMA_MCAN Event Map
          2. 10.3.2.2.2 PDMA_MCASP_G0 Event Map
          3. 10.3.2.2.3 PDMA_SPI_G0 Event Map
          4. 10.3.2.2.4 PDMA_SPI_G1 Event Map
          5. 10.3.2.2.5 PDMA_USART_G0 Event Map
          6. 10.3.2.2.6 PDMA_USART_G1 Event Map
          7. 10.3.2.2.7 PDMA_USART_G2 Event Map
    4. 10.4 Data Routing Unit (DRU)
      1. 10.4.1 DRU Overview
      2. 10.4.2 DRU Integration
      3. 10.4.3 DRU Functional Description
        1. 10.4.3.1 DRU Basic Functionality
          1. 10.4.3.1.1 Queues
          2. 10.4.3.1.2 Channel Configuration
            1. 10.4.3.1.2.1 Non-realtime Channel Configuration
            2. 10.4.3.1.2.2 Realtime Channel Configuration
          3. 10.4.3.1.3 TR Submission
            1. 10.4.3.1.3.1 Direct TR Submission
            2. 10.4.3.1.3.2 PSI-L TR Submission
          4. 10.4.3.1.4 TR Removal from Channel
          5. 10.4.3.1.5 Channel Tear Down
            1. 10.4.3.1.5.1 Tear Down Completion
        2. 10.4.3.2 DRU Virtualization
        3. 10.4.3.3 DRU Compression and Decompression
        4. 10.4.3.4 DRU Output Events
        5. 10.4.3.5 DRU Address Fetch Algorithm, TR and CR Formats
          1. 10.4.3.5.1 Transpose
          2. 10.4.3.5.2 Circular Buffering
        6. 10.4.3.6 DRU Firewalls
        7. 10.4.3.7 DRU Errors
        8. 10.4.3.8 DRU Configurations
  13. 11Time Sync
    1. 11.1 Time Sync Module (CPTS)
      1. 11.1.1 CPTS Overview
        1. 11.1.1.1 CPTS Features
      2. 11.1.2 CPTS Functional Description
        1. 11.1.2.1  CPTS Architecture
        2. 11.1.2.2  CPTS Initialization
        3. 11.1.2.3  32-bit Time Stamp Value
        4. 11.1.2.4  64-bit Time Stamp Value
          1. 11.1.2.4.1 64-Bit Timestamp Nudge
          2. 11.1.2.4.2 64-bit Timestamp PPM
        5. 11.1.2.5  Event FIFO
        6. 11.1.2.6  Timestamp Compare Output
          1. 11.1.2.6.1 Non-Toggle Mode
          2. 11.1.2.6.2 Toggle Mode
        7. 11.1.2.7  Timestamp Sync Output
        8. 11.1.2.8  Timestamp GENF Output
          1. 11.1.2.8.1 GENFn Nudge
          2. 11.1.2.8.2 GENFn PPM
        9. 11.1.2.9  Time Sync Events
          1. 11.1.2.9.1 Time Stamp Push Event
          2. 11.1.2.9.2 Time Stamp Counter Rollover Event (32-bit mode only)
          3. 11.1.2.9.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
          4. 11.1.2.9.4 Hardware Time Stamp Push Event
        10. 11.1.2.10 Timestamp Compare Event
        11. 11.1.2.11 CPTS Interrupt Handling
    2. 11.2 Timer Manager
      1. 11.2.1 Timer Manager Overview
        1. 11.2.1.1 Timer Manager Features
      2. 11.2.2 Timer Manager Functional Description
        1. 11.2.2.1 Timer Manager Function Overview
        2. 11.2.2.2 Timer Counter
          1. 11.2.2.2.1 Timer Counter Rollover
        3. 11.2.2.3 Timer Control Module (FSM)
        4. 11.2.2.4 Timer Reprogramming
        5. 11.2.2.5 Event FIFO
        6. 11.2.2.6 Output Event Lookup (OES RAM)
      3. 11.2.3 Timer Manager Programming Guide
        1. 11.2.3.1 Timer Manager Low-level Programming Models
          1. 11.2.3.1.1 Initialization Sequence
          2. 11.2.3.1.2 Real-time Operating Requirements
            1. 11.2.3.1.2.1 Timer Touch
            2. 11.2.3.1.2.2 Timer Disable
            3. 11.2.3.1.2.3 Timer Enable
          3. 11.2.3.1.3 Power Up/Power Down Sequence
    3. 11.3 Time Sync and Compare Events
      1. 11.3.1 Time Sync Architecture
        1. 11.3.1.1 Time Sync Architecture Overview
      2. 11.3.2 Time Sync Routers
        1. 11.3.2.1 Time Sync Routers Overview
      3. 11.3.3 Time Sync Event Sources
  14. 12Peripherals
    1. 12.1  General Connectivity Peripherals
      1. 12.1.1 Analog-to-Digital Converter (ADC)
        1. 12.1.1.1 ADC Overview
          1. 12.1.1.1.1 ADC Features
          2. 12.1.1.1.2 ADC Ports
        2. 12.1.1.2 ADC Environment
        3. 12.1.1.3 ADC Functional Description
          1. 12.1.1.3.1 ADC FSM Sequencer Functional Description
            1. 12.1.1.3.1.1 Step Enable
            2. 12.1.1.3.1.2 Step Configuration
              1. 12.1.1.3.1.2.1 One-Shot (Single) or Continuous Mode
              2. 12.1.1.3.1.2.2 Software- or Hardware-Enabled Steps
              3. 12.1.1.3.1.2.3 Averaging of Samples
              4. 12.1.1.3.1.2.4 Analog Multiplexer Input Select
              5. 12.1.1.3.1.2.5 Differential Control
              6. 12.1.1.3.1.2.6 FIFO Select
              7. 12.1.1.3.1.2.7 Range Check Interrupt Enable
            3. 12.1.1.3.1.3 Open Delay and Sample Delay
              1. 12.1.1.3.1.3.1 Open Delay
              2. 12.1.1.3.1.3.2 Sample Delay
            4. 12.1.1.3.1.4 Interrupts
            5. 12.1.1.3.1.5 Power Management
            6. 12.1.1.3.1.6 DMA Requests
          2. 12.1.1.3.2 ADC AFE Functional Description
            1. 12.1.1.3.2.1 AFE Functional Block Diagram
          3. 12.1.1.3.3 ADC FIFOs and DMA
            1. 12.1.1.3.3.1 FIFOs
            2. 12.1.1.3.3.2 DMA
          4. 12.1.1.3.4 ADC Error Correcting Code (ECC)
            1. 12.1.1.3.4.1 Testing ECC Error Injection
          5. 12.1.1.3.5 ADC Functional Debug Mode
        4. 12.1.1.4 ADC Programming Guide
          1. 12.1.1.4.1 ADC Low-Level Programming Models
            1. 12.1.1.4.1.1 During Operation
      2. 12.1.2 General-Purpose Interface (GPIO)
        1. 12.1.2.1 GPIO Overview
          1. 12.1.2.1.1 GPIO Features
          2. 12.1.2.1.2 GPIO Ports
        2. 12.1.2.2 GPIO Environment
        3. 12.1.2.3 GPIO Functional Description
          1. 12.1.2.3.1 GPIO Block Diagram
          2. 12.1.2.3.2 GPIO Function
          3. 12.1.2.3.3 GPIO Interrupt and Event Generation
            1. 12.1.2.3.3.1 Interrupt Enable (per Bank)
            2. 12.1.2.3.3.2 Trigger Configuration (per Bit)
            3. 12.1.2.3.3.3 Interrupt Status and Clear (per Bit)
          4. 12.1.2.3.4 GPIO Emulation Halt Operation
        4. 12.1.2.4 GPIO Programming Guide
          1. 12.1.2.4.1 GPIO Low-Level Programming Models
            1. 12.1.2.4.1.1 GPIO Operational Modes Configuration
              1. 12.1.2.4.1.1.1 GPIO Read Input Register
              2. 12.1.2.4.1.1.2 GPIO Set Bit Function
              3. 12.1.2.4.1.1.3 GPIO Clear Bit Function
      3. 12.1.3 Inter-Integrated Circuit (I2C) Interface
        1. 12.1.3.1 I2C Overview
          1. 12.1.3.1.1 I2C Features
          2. 12.1.3.1.2 I2C Ports
        2. 12.1.3.2 I2C Environment
        3. 12.1.3.3 I2C Functional Description
          1. 12.1.3.3.1 I2C Block Diagram
          2. 12.1.3.3.2 I2C Clocks
            1. 12.1.3.3.2.1 I2C Clocking
            2. 12.1.3.3.2.2 I2C Automatic Blocking of the I2C Clock Feature
          3. 12.1.3.3.3 I2C Software Reset
          4. 12.1.3.3.4 I2C Power Management
          5. 12.1.3.3.5 I2C Interrupt Requests
          6. 12.1.3.3.6 I2C Programmable Multitarget Channel Feature
          7. 12.1.3.3.7 I2C FIFO Management
            1. 12.1.3.3.7.1 I2C FIFO Interrupt Mode
            2. 12.1.3.3.7.2 I2C FIFO Polling Mode
            3. 12.1.3.3.7.3 I2C Draining Feature
          8. 12.1.3.3.8 I2C Noise Filter
          9. 12.1.3.3.9 I2C System Test Mode
        4. 12.1.3.4 I2C Programming Guide
          1. 12.1.3.4.1 I2C Low-Level Programming Models
            1. 12.1.3.4.1.1 I2C Programming Model
              1. 12.1.3.4.1.1.1 Main Program
                1. 12.1.3.4.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                2. 12.1.3.4.1.1.1.2 Initialize the I2C Controller
                3. 12.1.3.4.1.1.1.3 Configure Target Address and the Data Control Register
                4. 12.1.3.4.1.1.1.4 Initiate a Transfer
                5. 12.1.3.4.1.1.1.5 Receive Data
                6. 12.1.3.4.1.1.1.6 Transmit Data
              2. 12.1.3.4.1.1.2 Interrupt Subroutine Sequence
              3. 12.1.3.4.1.1.3 Programming Flow-Diagrams
      4. 12.1.4 Improved Inter-Integrated Circuit (I3C) Interface
        1. 12.1.4.1 I3C Overview
          1. 12.1.4.1.1 I3C Features
          2. 12.1.4.1.2 I3C Ports
        2. 12.1.4.2 I3C Environment
        3. 12.1.4.3 I3C Functional Description
          1. 12.1.4.3.1  I3C Block Diagram
          2. 12.1.4.3.2  I3C Clock Configuration
            1. 12.1.4.3.2.1 Setting Base Frequencies
            2. 12.1.4.3.2.2 Asymmetric Push-Pull SCL Timing
            3. 12.1.4.3.2.3 Open-Drain SCL Timing
            4. 12.1.4.3.2.4 Changing Programmed Frequencies
          3. 12.1.4.3.3  I3C Interrupt Requests
          4. 12.1.4.3.4  I3C Power Configuration
          5. 12.1.4.3.5  I3C Dynamic Address Management
          6. 12.1.4.3.6  I3C Retaining Registers Space
          7. 12.1.4.3.7  I3C Dynamic Address Assignment Procedure
          8. 12.1.4.3.8  I3C Sending CCC Messages
          9. 12.1.4.3.9  I3C In-Band Interrupt
            1. 12.1.4.3.9.1 Regular I3C Slave In-Band Interrupt
            2. 12.1.4.3.9.2 Current Master Takeover In-Band Interrupt
          10. 12.1.4.3.10 I3C Hot-Join Request
          11. 12.1.4.3.11 I3C Immediate Commands
          12. 12.1.4.3.12 I3C Host Commands
          13. 12.1.4.3.13 I3C Sending Private Data in SDR Messages
            1. 12.1.4.3.13.1 SDR Private Write Message
            2. 12.1.4.3.13.2 SDR Private Read Message
            3. 12.1.4.3.13.3 SDR Payload Length Adjustment
        4. 12.1.4.4 I3C Programming Guide
          1. 12.1.4.4.1 I3C Power-On Programming Model
          2. 12.1.4.4.2 I3C Static Devices Programming
          3. 12.1.4.4.3 I3C DAA Procedure Initiation
          4. 12.1.4.4.4 I3C SDR Write Message Programming Model
          5. 12.1.4.4.5 I3C SDR Read Message Programming Model
          6. 12.1.4.4.6 I3C DDR Write Message Programming Model
          7. 12.1.4.4.7 I3C DDR Read Message Programming Model
      5. 12.1.5 Multichannel Serial Peripheral Interface (MCSPI)
        1. 12.1.5.1 MCSPI Overview
          1. 12.1.5.1.1 SPI Features
          2. 12.1.5.1.2 MCSPI Ports
        2. 12.1.5.2 MCSPI Environment
        3. 12.1.5.3 MCSPI Functional Description
          1. 12.1.5.3.1 SPI Block Diagram
          2. 12.1.5.3.2 MCSPI Reset
          3. 12.1.5.3.3 MCSPI Controller Mode
            1. 12.1.5.3.3.1 Controller Mode Features
            2. 12.1.5.3.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 12.1.5.3.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 12.1.5.3.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 12.1.5.3.3.5 Single-Channel Controller Mode
              1. 12.1.5.3.3.5.1 Programming Tips When Switching to Another Channel
              2. 12.1.5.3.3.5.2 Force SPIEN[i] Mode
              3. 12.1.5.3.3.5.3 Turbo Mode
            6. 12.1.5.3.3.6 Start-Bit Mode
            7. 12.1.5.3.3.7 Chip-Select Timing Control
            8. 12.1.5.3.3.8 Programmable MCSPI Clock (SPICLK)
              1. 12.1.5.3.3.8.1 Clock Ratio Granularity
          4. 12.1.5.3.4 MCSPI Peripheral Mode
            1. 12.1.5.3.4.1 Dedicated Resources
            2. 12.1.5.3.4.2 Peripheral Transmit-and-Receive Mode
            3. 12.1.5.3.4.3 Peripheral Transmit-Only Mode
            4. 12.1.5.3.4.4 Peripheral Receive-Only Mode
          5. 12.1.5.3.5 MCSPI 3-Pin or 4-Pin Mode
          6. 12.1.5.3.6 MCSPI FIFO Buffer Management
            1. 12.1.5.3.6.1 Buffer Almost Full
            2. 12.1.5.3.6.2 Buffer Almost Empty
            3. 12.1.5.3.6.3 End of Transfer Management
            4. 12.1.5.3.6.4 Multiple MCSPI Word Access
            5. 12.1.5.3.6.5 First MCSPI Word Delay
          7. 12.1.5.3.7 MCSPI Interrupts
            1. 12.1.5.3.7.1 Interrupt Events in Controller Mode
              1. 12.1.5.3.7.1.1 TXx_EMPTY
              2. 12.1.5.3.7.1.2 TXx_UNDERFLOW
              3. 12.1.5.3.7.1.3 RXx_ FULL
              4. 12.1.5.3.7.1.4 End Of Word Count
            2. 12.1.5.3.7.2 Interrupt Events in Peripheral Mode
              1. 12.1.5.3.7.2.1 TXx_EMPTY
              2. 12.1.5.3.7.2.2 TXx_UNDERFLOW
              3. 12.1.5.3.7.2.3 RXx_FULL
              4. 12.1.5.3.7.2.4 RX0_OVERFLOW
              5. 12.1.5.3.7.2.5 End Of Word Count
            3. 12.1.5.3.7.3 Interrupt-Driven Operation
            4. 12.1.5.3.7.4 Polling
          8. 12.1.5.3.8 MCSPI DMA Requests
          9. 12.1.5.3.9 MCSPI Power Saving Management
            1. 12.1.5.3.9.1 Normal Mode
            2. 12.1.5.3.9.2 Idle Mode
              1. 12.1.5.3.9.2.1 Force-Idle Mode
        4. 12.1.5.4 MCSPI Programming Guide
          1. 12.1.5.4.1 MCSPI Operational Mode Configuration
            1. 12.1.5.4.1.1 MCSPI Operational Modes
              1. 12.1.5.4.1.1.1 Common Transfer Sequence
              2. 12.1.5.4.1.1.2 End of Transfer Sequences
              3. 12.1.5.4.1.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 12.1.5.4.1.1.4 Transmit-Only (Controller and Peripheral)
                1. 12.1.5.4.1.1.4.1 Based on Interrupt Requests
                2. 12.1.5.4.1.1.4.2 Based on DMA Write Requests
              5. 12.1.5.4.1.1.5 Controller Normal Receive-Only
                1. 12.1.5.4.1.1.5.1 Based on Interrupt Requests
                2. 12.1.5.4.1.1.5.2 Based on DMA Read Requests
              6. 12.1.5.4.1.1.6 Controller Turbo Receive-Only
                1. 12.1.5.4.1.1.6.1 Based on Interrupt Requests
                2. 12.1.5.4.1.1.6.2 Based on DMA Read Requests
              7. 12.1.5.4.1.1.7 Peripheral Receive-Only
              8. 12.1.5.4.1.1.8 Transfer Procedures With FIFO
                1. 12.1.5.4.1.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 12.1.5.4.1.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 12.1.5.4.1.1.8.3 Transmit-and-Receive With Word Count
                4. 12.1.5.4.1.1.8.4 Transmit-and-Receive Without Word Count
                5. 12.1.5.4.1.1.8.5 Transmit-Only
                6. 12.1.5.4.1.1.8.6 Receive-Only With Word Count
                7. 12.1.5.4.1.1.8.7 Receive-Only Without Word Count
              9. 12.1.5.4.1.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.5.4.1.1.9.1 Receive-Only Procedure – Polling Method
                2. 12.1.5.4.1.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.5.4.1.1.9.3 Transmit-Only Procedure – Polling Method
                4. 12.1.5.4.1.1.9.4 Transmit-and-Receive Procedure – Polling Method
      6. 12.1.6 Universal Asynchronous Receiver/Transmitter (UART)
        1. 12.1.6.1 UART Overview
          1. 12.1.6.1.1 UART Features
          2. 12.1.6.1.2 IrDA Features
          3. 12.1.6.1.3 CIR Features
          4. 12.1.6.1.4 UART Ports
        2. 12.1.6.2 UART Environment
        3. 12.1.6.3 UART Functional Description
          1. 12.1.6.3.1 UART Block Diagram
          2. 12.1.6.3.2 UART Clock Configuration
          3. 12.1.6.3.3 UART Software Reset
            1. 12.1.6.3.3.1 Independent TX/RX
          4. 12.1.6.3.4 UART Power Management
            1. 12.1.6.3.4.1 UART Mode Power Management
              1. 12.1.6.3.4.1.1 Module Power Saving
              2. 12.1.6.3.4.1.2 System Power Saving
            2. 12.1.6.3.4.2 IrDA Mode Power Management
              1. 12.1.6.3.4.2.1 Module Power Saving
              2. 12.1.6.3.4.2.2 System Power Saving
            3. 12.1.6.3.4.3 CIR Mode Power Management
              1. 12.1.6.3.4.3.1 Module Power Saving
              2. 12.1.6.3.4.3.2 System Power Saving
            4. 12.1.6.3.4.4 Local Power Management
          5. 12.1.6.3.5 UART Interrupt Requests
            1. 12.1.6.3.5.1 UART Mode Interrupt Management
              1. 12.1.6.3.5.1.1 UART Interrupts
              2. 12.1.6.3.5.1.2 Wake-Up Interrupt
            2. 12.1.6.3.5.2 IrDA Mode Interrupt Management
              1. 12.1.6.3.5.2.1 IrDA Interrupts
              2. 12.1.6.3.5.2.2 Wake-Up Interrupts
            3. 12.1.6.3.5.3 CIR Mode Interrupt Management
              1. 12.1.6.3.5.3.1 CIR Interrupts
              2. 12.1.6.3.5.3.2 Wake-Up Interrupts
          6. 12.1.6.3.6 UART FIFO Management
            1. 12.1.6.3.6.1 FIFO Trigger
              1. 12.1.6.3.6.1.1 Transmit FIFO Trigger
              2. 12.1.6.3.6.1.2 Receive FIFO Trigger
            2. 12.1.6.3.6.2 FIFO Interrupt Mode
            3. 12.1.6.3.6.3 FIFO Polled Mode Operation
            4. 12.1.6.3.6.4 FIFO DMA Mode Operation
              1. 12.1.6.3.6.4.1 DMA sequence to disable TX DMA
              2. 12.1.6.3.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 12.1.6.3.6.4.3 DMA Transmission
              4. 12.1.6.3.6.4.4 DMA Reception
          7. 12.1.6.3.7 UART Mode Selection
            1. 12.1.6.3.7.1 Register Access Modes
              1. 12.1.6.3.7.1.1 Operational Mode and Configuration Modes
              2. 12.1.6.3.7.1.2 Register Access Submode
              3. 12.1.6.3.7.1.3 Registers Available for the Register Access Modes
            2. 12.1.6.3.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 12.1.6.3.7.2.1 Registers Available for the UART Function
              2. 12.1.6.3.7.2.2 Registers Available for the IrDA Function
              3. 12.1.6.3.7.2.3 Registers Available for the CIR Function
          8. 12.1.6.3.8 UART Protocol Formatting
            1. 12.1.6.3.8.1 UART Mode
              1. 12.1.6.3.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 12.1.6.3.8.1.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.3.8.1.3 UART Data Formatting
                1. 12.1.6.3.8.1.3.1 Frame Formatting
                2. 12.1.6.3.8.1.3.2 Hardware Flow Control
                3. 12.1.6.3.8.1.3.3 Software Flow Control
                  1. 1.6.3.8.1.3.3.1 Receive (RX)
                  2. 1.6.3.8.1.3.3.2 Transmit (TX)
                4. 12.1.6.3.8.1.3.4 Autobauding Modes
                5. 12.1.6.3.8.1.3.5 Error Detection
                6. 12.1.6.3.8.1.3.6 Overrun During Receive
                7. 12.1.6.3.8.1.3.7 Time-Out and Break Conditions
                  1. 1.6.3.8.1.3.7.1 Time-Out Counter
                  2. 1.6.3.8.1.3.7.2 Break Condition
            2. 12.1.6.3.8.2 RS-485 Mode
              1. 12.1.6.3.8.2.1 RS-485 External Transceiver Direction Control
            3. 12.1.6.3.8.3 IrDA Mode
              1. 12.1.6.3.8.3.1 IrDA Clock Generation: Baud Generator
              2. 12.1.6.3.8.3.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.3.8.3.3 IrDA Data Formatting
                1. 12.1.6.3.8.3.3.1  IR RX Polarity Control
                2. 12.1.6.3.8.3.3.2  IrDA Reception Control
                3. 12.1.6.3.8.3.3.3  IR Address Checking
                4. 12.1.6.3.8.3.3.4  Frame Closing
                5. 12.1.6.3.8.3.3.5  Store and Controlled Transmission
                6. 12.1.6.3.8.3.3.6  Error Detection
                7. 12.1.6.3.8.3.3.7  Underrun During Transmission
                8. 12.1.6.3.8.3.3.8  Overrun During Receive
                9. 12.1.6.3.8.3.3.9  Status FIFO
                10. 12.1.6.3.8.3.3.10 Multi-drop Parity Mode with Address Match
                11. 12.1.6.3.8.3.3.11 Time-guard
              4. 12.1.6.3.8.3.4 SIR Mode Data Formatting
                1. 12.1.6.3.8.3.4.1 Abort Sequence
                2. 12.1.6.3.8.3.4.2 Pulse Shaping
                3. 12.1.6.3.8.3.4.3 SIR Free Format Programming
              5. 12.1.6.3.8.3.5 MIR and FIR Mode Data Formatting
            4. 12.1.6.3.8.4 CIR Mode
              1. 12.1.6.3.8.4.1 CIR Mode Clock Generation
              2. 12.1.6.3.8.4.2 CIR Data Formatting
                1. 12.1.6.3.8.4.2.1 IR RX Polarity Control
                2. 12.1.6.3.8.4.2.2 CIR Transmission
                3. 12.1.6.3.8.4.2.3 CIR Reception
        4. 12.1.6.4 UART Programming Guide
          1. 12.1.6.4.1 UART Mode selection
          2. 12.1.6.4.2 UART Submode selection
          3. 12.1.6.4.3 UART Load FIFO trigger and DMA mode settings
            1. 12.1.6.4.3.1 DMA mode Settings
            2. 12.1.6.4.3.2 FIFO Trigger Settings
          4. 12.1.6.4.4 UART Protocol, Baud rate and interrupt settings
            1. 12.1.6.4.4.1 Baud rate settings
            2. 12.1.6.4.4.2 Interrupt settings
            3. 12.1.6.4.4.3 Protocol settings
            4. 12.1.6.4.4.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 12.1.6.4.4.5 UART Multi-drop Parity Address Match Mode Configuration
          5. 12.1.6.4.5 UART Hardware and Software Flow Control Configuration
            1. 12.1.6.4.5.1 Hardware Flow Control Configuration
            2. 12.1.6.4.5.2 Software Flow Control Configuration
          6. 12.1.6.4.6 IrDA Programming Model
            1. 12.1.6.4.6.1 SIR mode
              1. 12.1.6.4.6.1.1 Receive
              2. 12.1.6.4.6.1.2 Transmit
            2. 12.1.6.4.6.2 MIR mode
              1. 12.1.6.4.6.2.1 Receive
              2. 12.1.6.4.6.2.2 Transmit
            3. 12.1.6.4.6.3 FIR mode
              1. 12.1.6.4.6.3.1 Receive
              2. 12.1.6.4.6.3.2 Transmit
    2. 12.2  High-speed Serial Interfaces
      1. 12.2.1 Gigabit Ethernet MAC (CPSW)
        1. 12.2.1.1 CPSW Programming Guide
          1. 12.2.1.1.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.1.1.2 CPSW Reset
          3. 12.2.1.1.3 MDIO Software Interface
            1. 12.2.1.1.3.1 Initializing the MDIO Module
            2. 12.2.1.1.3.2 Writing Data To a PHY Register
            3. 12.2.1.1.3.3 Reading Data From a PHY Register
      2. 12.2.2 Peripheral Component Interconnect Express (PCIe) Subsystem
        1. 12.2.2.1 PCIe Subsystem Overview
          1. 12.2.2.1.1 PCIe Subsystem Features
          2. 12.2.2.1.2 PCIe Subsystem Ports
        2. 12.2.2.2 PCIe Environment
        3. 12.2.2.3 PCIe Subsystem Functional Description
          1. 12.2.2.3.1  PCIe Subsystem Block Diagram
            1. 12.2.2.3.1.1 PCIe Core Module
            2. 12.2.2.3.1.2 PCIe PHY Interface
            3. 12.2.2.3.1.3 CBA Infrastructure
            4. 12.2.2.3.1.4 VBUSM to AXI Bridges
            5. 12.2.2.3.1.5 AXI to VBUSM Bridges
            6. 12.2.2.3.1.6 VBUSP to APB Bridge
            7. 12.2.2.3.1.7 Custom Logic
          2. 12.2.2.3.2  PCIe Subsystem Reset Schemes
            1. 12.2.2.3.2.1 PCIe Conventional Reset
            2. 12.2.2.3.2.2 PCIe Function Level Reset
            3. 12.2.2.3.2.3 PCIe Reset Isolation
              1. 12.2.2.3.2.3.1 Root Port Reset with Device Not Reset
              2. 12.2.2.3.2.3.2 Device Reset with Root Port Not Reset
              3. 12.2.2.3.2.3.3 End Point Device Reset with Root Port Not Reset
              4. 12.2.2.3.2.3.4 Device Reset with End Point Device Not Reset
            4. 12.2.2.3.2.4 PCIe Reset Limitations
            5. 12.2.2.3.2.5 PCIe Reset Requirements
          3. 12.2.2.3.3  PCIe Subsystem Power Management
            1. 12.2.2.3.3.1 CBA Power Management
          4. 12.2.2.3.4  PCIe Subsystem Interrupts
            1. 12.2.2.3.4.1 Interrupts Aggregation
            2. 12.2.2.3.4.2 Interrupt Generation in EP Mode
              1. 12.2.2.3.4.2.1 Legacy Interrupt Generation in EP Mode
              2. 12.2.2.3.4.2.2 MSI and MSI-X Interrupt Generation
            3. 12.2.2.3.4.3 Interrupt Reception in EP Mode
              1. 12.2.2.3.4.3.1 PCIe Core Downstream Interrupts
              2. 12.2.2.3.4.3.2 PCIe Core Function Level Reset Interrupts
              3. 12.2.2.3.4.3.3 PCIe Core Power Management Event Interrupts
              4. 12.2.2.3.4.3.4 PCIe Core Hot Reset Request Interrupt
              5. 12.2.2.3.4.3.5 PTM Valid Interrupt
            4. 12.2.2.3.4.4 Interrupt Generation in RP Mode
            5. 12.2.2.3.4.5 Interrupt Reception in RP Mode
              1. 12.2.2.3.4.5.1 PCIe Legacy Interrupt Reception in RP Mode
              2. 12.2.2.3.4.5.2 MSI/MSI-X Interrupt Reception in RP Mode
              3. 12.2.2.3.4.5.3 Advanced Error Reporting Interrupt
            6. 12.2.2.3.4.6 Common Interrupt Reception in RP and EP Modes
              1. 12.2.2.3.4.6.1 PCIe Local Interrupt
              2. 12.2.2.3.4.6.2 PHY Interrupt
              3. 12.2.2.3.4.6.3 Link down Interrupt
              4. 12.2.2.3.4.6.4 Transaction Error Interrupts
              5. 12.2.2.3.4.6.5 Power Management Event Interrupt
              6. 12.2.2.3.4.6.6 Active Internal Diagnostics Interrupts
            7. 12.2.2.3.4.7 ECC Aggregator Interrupts
            8. 12.2.2.3.4.8 CPTS Interrupt
          5. 12.2.2.3.5  PCIe Subsystem DMA Support
            1. 12.2.2.3.5.1 PCIe DMA Support in RP Mode
            2. 12.2.2.3.5.2 PCIe DMA Support in EP Mode
          6. 12.2.2.3.6  PCIe Subsystem Transactions
            1. 12.2.2.3.6.1 PCIe Supported Transactions
            2. 12.2.2.3.6.2 PCIe Transaction Limitations
          7. 12.2.2.3.7  PCIe Subsystem Address Translation
            1. 12.2.2.3.7.1 PCIe Inbound Address Translation
              1. 12.2.2.3.7.1.1 Root Port Inbound PCIe to AXI Address Translation
              2. 12.2.2.3.7.1.2 End Point Inbound PCIe to AXI Address Translation
            2. 12.2.2.3.7.2 PCIe Outbound Address Translation
              1. 12.2.2.3.7.2.1 PCIe Outbound Address Translation Bypass
          8. 12.2.2.3.8  PCIe Subsystem Virtualization Support
            1. 12.2.2.3.8.1 End Point SR-IOV Support
            2. 12.2.2.3.8.2 Root Port ATS Support
            3. 12.2.2.3.8.3 VirtID Mapping
          9. 12.2.2.3.9  PCIe Subsystem Quality-of-Service (QoS)
          10. 12.2.2.3.10 PCIe Subsystem Precision Time Measurement (PTM)
          11. 12.2.2.3.11 PCIe Subsystem Loopback
            1. 12.2.2.3.11.1 PCIe PIPE Loopback
              1. 12.2.2.3.11.1.1 PIPE Loopback Master Mode
              2. 12.2.2.3.11.1.2 PIPE Loopback Slave Mode
          12. 12.2.2.3.12 PCIe Subsystem Error Handling
            1. 12.2.2.3.12.1 PCIe AXI to/from VBUSM Bus Error Mapping
          13. 12.2.2.3.13 PCIe Subsystem Internal Diagnostics Features
            1. 12.2.2.3.13.1 PCIe Parity
            2. 12.2.2.3.13.2 ECC Aggregators
            3. 12.2.2.3.13.3 RAM ECC Inversion
          14. 12.2.2.3.14 LTSSM State Encoding
      3. 12.2.3 Universal Serial Bus (USB) Subsystem
        1. 12.2.3.1 USB Overview
          1. 12.2.3.1.1 USB Features
          2. 12.2.3.1.2 USB Ports
          3. 12.2.3.1.3 USB Terminology
        2. 12.2.3.2 USB Environment
        3. 12.2.3.3 USB Functional Description
          1. 12.2.3.3.1 USB Type-C Connector Support
          2. 12.2.3.3.2 USB Controller Reset
          3. 12.2.3.3.3 Overcurrent Detection
          4. 12.2.3.3.4 Top-Level Initialization Sequence
      4. 12.2.4 Serializer/Deserializer (SerDes)
        1. 12.2.4.1 SerDes Overview
          1. 12.2.4.1.1 SerDes Features
          2. 12.2.4.1.2 SerDes Ports
          3. 12.2.4.1.3 Industry Standards Compatibility
        2. 12.2.4.2 SerDes Environment
          1. 12.2.4.2.1 SerDes I/Os
        3. 12.2.4.3 SerDes Integration
          1. 12.2.4.3.1 WIZ Settings
            1. 12.2.4.3.1.1 Interface Selection
            2. 12.2.4.3.1.2 ACSPCIe Reference Clock Selection
        4. 12.2.4.4 SerDes Functional Description
          1. 12.2.4.4.1 SerDes Block Diagram
    3. 12.3  Memory Interfaces
      1. 12.3.1 Flash Subsystem (FSS)
        1. 12.3.1.1 FSS Overview
          1. 12.3.1.1.1 FSS Features
          2. 12.3.1.1.2 Flash Ports
        2. 12.3.1.2 FSS Environment
        3. 12.3.1.3 FSS Functional Description
          1. 12.3.1.3.1 FSS Block Diagram
          2. 12.3.1.3.2 FSS ECC Support
          3. 12.3.1.3.3 FSS Modes of Operation
          4. 12.3.1.3.4 FSS Memory Regions
        4. 12.3.1.4 FSS Programming Guide
          1. 12.3.1.4.1 FSS Initialization Sequence
          2. 12.3.1.4.2 FSS Real-Time Operation
          3. 12.3.1.4.3 FSS Power Up/Down Sequence
      2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
        1. 12.3.2.1 OSPI Overview
          1. 12.3.2.1.1 OSPI Features
          2. 12.3.2.1.2 OSPI Ports
        2. 12.3.2.2 OSPI Environment
        3. 12.3.2.3 OSPI Functional Description
          1. 12.3.2.3.1  OSPI Block Diagram
            1. 12.3.2.3.1.1 Data Slave Interface
            2. 12.3.2.3.1.2 Configuration Slave Interface
            3. 12.3.2.3.1.3 OSPI Clock Domains
          2. 12.3.2.3.2  OSPI Modes
            1. 12.3.2.3.2.1 Read Data Capture
              1. 12.3.2.3.2.1.1 Mechanisms of Data Capturing
              2. 12.3.2.3.2.1.2 Data Capturing Mechanism Using Taps
              3. 12.3.2.3.2.1.3 Data Capturing Mechanism Using PHY Module
            2. 12.3.2.3.2.2 External Pull Down on DQS
          3. 12.3.2.3.3  OSPI Power Management
          4. 12.3.2.3.4  Auto HW Polling
          5. 12.3.2.3.5  Flash Reset
          6. 12.3.2.3.6  OSPI Memory Regions
          7. 12.3.2.3.7  OSPI Interrupt Requests
          8. 12.3.2.3.8  OSPI Data Interface
            1. 12.3.2.3.8.1 Data Interface Address Remapping
            2. 12.3.2.3.8.2 Write Protection
            3. 12.3.2.3.8.3 Access Forwarding
          9. 12.3.2.3.9  OSPI Direct Access Controller (DAC)
          10. 12.3.2.3.10 OSPI Indirect Access Controller (INDAC)
            1. 12.3.2.3.10.1 Indirect Read Controller
              1. 12.3.2.3.10.1.1 Indirect Read Transfer Process
            2. 12.3.2.3.10.2 Indirect Write Controller
              1. 12.3.2.3.10.2.1 Indirect Write Transfer Process
            3. 12.3.2.3.10.3 Indirect Access Queuing
            4. 12.3.2.3.10.4 Consecutive Writes and Reads Using Indirect Transfers
            5. 12.3.2.3.10.5 Accessing the SRAM
          11. 12.3.2.3.11 OSPI Software-Triggered Instruction Generator (STIG)
            1. 12.3.2.3.11.1 Servicing a STIG Request
            2. 12.3.2.3.11.2 2262
          12. 12.3.2.3.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
          13. 12.3.2.3.13 OSPI Command Translation
          14. 12.3.2.3.14 Selecting the Flash Instruction Type
          15. 12.3.2.3.15 OSPI Data Integrity
          16. 12.3.2.3.16 OSPI PHY Module
            1. 12.3.2.3.16.1 PHY Pipeline Mode
            2. 12.3.2.3.16.2 Read Data Capturing by the PHY Module
        4. 12.3.2.4 OSPI Programming Guide
          1. 12.3.2.4.1 Configuring the OSPI Controller for Use After Reset
          2. 12.3.2.4.2 Configuring the OSPI Controller for Optimal Use
          3. 12.3.2.4.3 Using the Flash Command Control Register (STIG Operation)
          4. 12.3.2.4.4 Using SPI Legacy Mode
          5. 12.3.2.4.5 Entering XIP Mode from POR
          6. 12.3.2.4.6 Entering XIP Mode Otherwise
          7. 12.3.2.4.7 Exiting XIP Mode
      3. 12.3.3 HyperBus Interface
        1. 12.3.3.1 HyperBus Overview
          1. 12.3.3.1.1 HyperBus Features
          2. 12.3.3.1.2 Hyperbus Ports
        2. 12.3.3.2 HyperBus Environment
        3. 12.3.3.3 HyperBus Functional Description
          1. 12.3.3.3.1 HyperBus Interrupts
          2. 12.3.3.3.2 HyperBus ECC Support
            1. 12.3.3.3.2.1 ECC Aggregator
          3. 12.3.3.3.3 HyperBus Internal FIFOs
          4. 12.3.3.3.4 HyperBus Data Regions
          5. 12.3.3.3.5 HyperBus True Continuous Read (TCR) Mode
        4. 12.3.3.4 HyperBus Programming Guide
          1. 12.3.3.4.1 HyperBus Initialization Sequence
            1. 12.3.3.4.1.1 HyperFlash Access
            2. 12.3.3.4.1.2 HyperRAM Access
          2. 12.3.3.4.2 HyperBus Real-time Operating Requirements
          3. 12.3.3.4.3 HyperBus Power Up/Down Sequence
      4. 12.3.4 General-Purpose Memory Controller (GPMC)
        1. 12.3.4.1 GPMC Overview
          1. 12.3.4.1.1 GPMC Features
          2. 12.3.4.1.2 GPMC Ports
        2. 12.3.4.2 GPMC Environment
        3. 12.3.4.3 GPMC Functional Description
          1. 12.3.4.3.1  GPMC Block Diagram
          2. 12.3.4.3.2  GPMC Clock Configuration
          3. 12.3.4.3.3  GPMC Power Management
          4. 12.3.4.3.4  GPMC Interrupt Requests
          5. 12.3.4.3.5  GPMC Interconnect Port Interface
          6. 12.3.4.3.6  GPMC Address and Data Bus
            1. 12.3.4.3.6.1 GPMC I/O Configuration Setting
          7. 12.3.4.3.7  GPMC Address Decoder and Chip-Select Configuration
            1. 12.3.4.3.7.1 Chip-Select Base Address and Region Size
            2. 12.3.4.3.7.2 Access Protocol
              1. 12.3.4.3.7.2.1 Supported Devices
              2. 12.3.4.3.7.2.2 Access Size Adaptation and Device Width
              3. 12.3.4.3.7.2.3 Address/Data-Multiplexing Interface
            3. 12.3.4.3.7.3 External Signals
              1. 12.3.4.3.7.3.1 WAIT Pin Monitoring Control
                1. 12.3.4.3.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 12.3.4.3.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 12.3.4.3.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 12.3.4.3.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 12.3.4.3.7.3.1.5 Wait With NAND Device
                6. 12.3.4.3.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.4.3.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.4.3.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.4.3.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 12.3.4.3.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 12.3.4.3.7.3.2 DIR Pin
              3. 12.3.4.3.7.3.3 Reset
              4. 12.3.4.3.7.3.4 Write Protect Signal (nWP)
              5. 12.3.4.3.7.3.5 Byte Enable (nBE1/nBE0)
            4. 12.3.4.3.7.4 Error Handling
          8. 12.3.4.3.8  GPMC Timing Setting
            1. 12.3.4.3.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 12.3.4.3.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 12.3.4.3.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 12.3.4.3.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 12.3.4.3.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 12.3.4.3.8.6  GPMC_CLKOUT
            7. 12.3.4.3.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 12.3.4.3.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 12.3.4.3.8.8.1 Access Time on Read Access
              2. 12.3.4.3.8.8.2 Access Time on Write Access
            9. 12.3.4.3.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 12.3.4.3.8.9.1 Page Burst Access Time on Read Access
              2. 12.3.4.3.8.9.2 Page Burst Access Time on Write Access
            10. 12.3.4.3.8.10 Bus Keeping Support
          9. 12.3.4.3.9  GPMC NOR Access Description
            1. 12.3.4.3.9.1 Asynchronous Access Description
              1. 12.3.4.3.9.1.1 Access on Address/Data Multiplexed Devices
                1. 12.3.4.3.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 12.3.4.3.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 12.3.4.3.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 12.3.4.3.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 12.3.4.3.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 12.3.4.3.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 12.3.4.3.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 12.3.4.3.9.2 Synchronous Access Description
              1. 12.3.4.3.9.2.1 Synchronous Single Read
              2. 12.3.4.3.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 12.3.4.3.9.2.3 Synchronous Single Write
              4. 12.3.4.3.9.2.4 Synchronous Multiple (Burst) Write
            3. 12.3.4.3.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 12.3.4.3.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 12.3.4.3.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 12.3.4.3.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 12.3.4.3.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 12.3.4.3.9.4 Page and Burst Support
            5. 12.3.4.3.9.5 System Burst vs External Device Burst Support
          10. 12.3.4.3.10 GPMC pSRAM Access Specificities
          11. 12.3.4.3.11 GPMC NAND Access Description
            1. 12.3.4.3.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 12.3.4.3.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 12.3.4.3.11.1.2 NAND Device Command and Address Phase Control
              3. 12.3.4.3.11.1.3 Command Latch Cycle
              4. 12.3.4.3.11.1.4 Address Latch Cycle
              5. 12.3.4.3.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 12.3.4.3.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 12.3.4.3.11.1.7 Read and Write Access Size Adaptation
                1. 12.3.4.3.11.1.7.1 8-Bit-Wide NAND Device
                2. 12.3.4.3.11.1.7.2 16-Bit-Wide NAND Device
            2. 12.3.4.3.11.2 NAND Device-Ready Pin
              1. 12.3.4.3.11.2.1 Ready Pin Monitored by Software Polling
              2. 12.3.4.3.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 12.3.4.3.11.3 ECC Calculator
              1. 12.3.4.3.11.3.1 Hamming Code
                1. 12.3.4.3.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 12.3.4.3.11.3.1.2 ECC Enabling
                3. 12.3.4.3.11.3.1.3 ECC Computation
                4. 12.3.4.3.11.3.1.4 ECC Comparison and Correction
                5. 12.3.4.3.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 12.3.4.3.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 12.3.4.3.11.3.2 BCH Code
                1. 12.3.4.3.11.3.2.1 Requirements
                2. 12.3.4.3.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.4.3.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.4.3.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.4.3.11.3.2.2.3 Wrapping Modes
                    1. 4.3.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 4.3.11.3.2.2.3.2  Mode 0x1
                    3. 4.3.11.3.2.2.3.3  Mode 0xA (10)
                    4. 4.3.11.3.2.2.3.4  Mode 0x2
                    5. 4.3.11.3.2.2.3.5  Mode 0x3
                    6. 4.3.11.3.2.2.3.6  Mode 0x7
                    7. 4.3.11.3.2.2.3.7  Mode 0x8
                    8. 4.3.11.3.2.2.3.8  Mode 0x4
                    9. 4.3.11.3.2.2.3.9  Mode 0x9
                    10. 4.3.11.3.2.2.3.10 Mode 0x5
                    11. 4.3.11.3.2.2.3.11 Mode 0xB (11)
                    12. 4.3.11.3.2.2.3.12 Mode 0x6
                3. 12.3.4.3.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.4.3.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.4.3.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.4.3.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 12.3.4.3.11.4 Prefetch and Write-Posting Engine
              1. 12.3.4.3.11.4.1 General Facts About the Engine Configuration
              2. 12.3.4.3.11.4.2 Prefetch Mode
              3. 12.3.4.3.11.4.3 FIFO Control in Prefetch Mode
              4. 12.3.4.3.11.4.4 Write-Posting Mode
              5. 12.3.4.3.11.4.5 FIFO Control in Write-Posting Mode
              6. 12.3.4.3.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 12.3.4.3.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 12.3.4.3.12 GPMC Memory Regions
          13. 12.3.4.3.13 GPMC Use Cases and Tips
            1. 12.3.4.3.13.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 12.3.4.3.13.1.1 External Memory Attached to the GPMC Module
              2. 12.3.4.3.13.1.2 Typical GPMC Setup
                1. 12.3.4.3.13.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 12.3.4.3.13.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 12.3.4.3.13.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 12.3.4.3.13.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 12.3.4.3.13.2.1 Supported Memories or Devices
                1. 12.3.4.3.13.2.1.1 Memory Pin Multiplexing
                2. 12.3.4.3.13.2.1.2 NAND Interface Protocol
                3. 12.3.4.3.13.2.1.3 NOR Interface Protocol
                4. 12.3.4.3.13.2.1.4 Other Technologies
        4. 12.3.4.4 GPMC Basic Programming Model
          1. 12.3.4.4.1 GPMC High-Level Programming Model Overview
          2. 12.3.4.4.2 GPMC Initialization
          3. 12.3.4.4.3 GPMC Configuration in NOR Mode
          4. 12.3.4.4.4 GPMC Configuration in NAND Mode
          5. 12.3.4.4.5 Set Memory Access
          6. 12.3.4.4.6 GPMC Timing Parameters
            1. 12.3.4.4.6.1 GPMC Timing Parameters Formulas
              1. 12.3.4.4.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 12.3.4.4.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 12.3.4.4.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
      5. 12.3.5 Error Location Module (ELM)
        1. 12.3.5.1 ELM Overview
          1. 12.3.5.1.1 ELM Features
          2. 12.3.5.1.2 ELM Ports
        2. 12.3.5.2 ELM Functional Description
          1. 12.3.5.2.1 ELM Software Reset
          2. 12.3.5.2.2 ELM Power Management
          3. 12.3.5.2.3 ELM Interrupt Requests
          4. 12.3.5.2.4 ELM Processing Initialization
          5. 12.3.5.2.5 ELM Processing Sequence
          6. 12.3.5.2.6 ELM Processing Completion
        3. 12.3.5.3 ELM Basic Programming Model
          1. 12.3.5.3.1 ELM Low-Level Programming Model
            1. 12.3.5.3.1.1 Processing Initialization
            2. 12.3.5.3.1.2 Read Results
            3. 12.3.5.3.1.3 2462
          2. 12.3.5.3.2 Use Case: ELM Used in Continuous Mode
          3. 12.3.5.3.3 Use Case: ELM Used in Page Mode
      6. 12.3.6 Multi-Media Card Secure Digital (MMCSD) Interface
        1. 12.3.6.1 MMCSD Overview
          1. 12.3.6.1.1 MMCSD Features
          2. 12.3.6.1.2 MMCSD Ports
        2. 12.3.6.2 MMCSD Environment
        3. 12.3.6.3 MMCSD Functional Description
          1. 12.3.6.3.1 Block Diagram
          2. 12.3.6.3.2 Memory Regions
          3. 12.3.6.3.3 Interrupt Requests
          4. 12.3.6.3.4 ECC Support
            1. 12.3.6.3.4.1 ECC Aggregator
          5. 12.3.6.3.5 Advanced DMA
        4. 12.3.6.4 MMCSD Programming Guide
          1. 12.3.6.4.1 Sequences
            1. 12.3.6.4.1.1  SD Card Detection
            2. 12.3.6.4.1.2  SD Clock Control
              1. 12.3.6.4.1.2.1 Internal Clock Setup Sequence
              2. 12.3.6.4.1.2.2 SD Clock Supply and Stop Sequence
              3. 12.3.6.4.1.2.3 SD Clock Frequency Change Sequence
            3. 12.3.6.4.1.3  SD Bus Power Control
            4. 12.3.6.4.1.4  Changing Bus Width
            5. 12.3.6.4.1.5  Timeout Setting on DAT Line
            6. 12.3.6.4.1.6  Card Initialization and Identification (for SD I/F)
              1. 12.3.6.4.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
            7. 12.3.6.4.1.7  SD Transaction Generation
              1. 12.3.6.4.1.7.1 Transaction Control without Data Transfer Using DAT Line
                1. 12.3.6.4.1.7.1.1 The Sequence to Issue a SD Command
                2. 12.3.6.4.1.7.1.2 The Sequence to Finalize a Command
              2. 12.3.6.4.1.7.2 Transaction Control with Data Transfer Using DAT Line
                1. 12.3.6.4.1.7.2.1 Not using DMA
                2. 12.3.6.4.1.7.2.2 Using SDMA
                3. 12.3.6.4.1.7.2.3 Using ADMA
            8. 12.3.6.4.1.8  Abort Transaction
              1. 12.3.6.4.1.8.1 Asynchronous Abort
              2. 12.3.6.4.1.8.2 Synchronous Abort
            9. 12.3.6.4.1.9  Changing Bus Speed Mode
            10. 12.3.6.4.1.10 Error Recovery
              1. 12.3.6.4.1.10.1 Error Interrupt Recovery
              2. 12.3.6.4.1.10.2 Auto CMD12 Error Recovery
            11. 12.3.6.4.1.11 Wakeup Control (Optional)
            12. 12.3.6.4.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
              1. 12.3.6.4.1.12.1 Suspend Sequence
              2. 12.3.6.4.1.12.2 Resume Sequence
              3. 12.3.6.4.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
              4. 12.3.6.4.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
          2. 12.3.6.4.2 Driver Flow Sequence
            1. 12.3.6.4.2.1 Host Controller Setup and Card Detection
              1. 12.3.6.4.2.1.1 Host Controller Setup Sequence
              2. 12.3.6.4.2.1.2 Card Interface Detection Sequence
            2. 12.3.6.4.2.2 Boot Operation
              1. 12.3.6.4.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
              2. 12.3.6.4.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
              3. 12.3.6.4.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
            3. 12.3.6.4.2.3 Retuning procedure (For Legacy Interface)
              1. 12.3.6.4.2.3.1 Sampling Clock Tuning
              2. 12.3.6.4.2.3.2 Tuning Modes
              3. 12.3.6.4.2.3.3 Re-Tuning Mode 2
            4. 12.3.6.4.2.4 Command Queuing Driver Flow Sequence
              1. 12.3.6.4.2.4.1 Command Queuing Initialization Sequence
              2. 12.3.6.4.2.4.2 Task Issuance Sequence
              3. 12.3.6.4.2.4.3 Task Execution and Completion Sequence
              4. 12.3.6.4.2.4.4 Task Discard and Clear Sequence
              5. 12.3.6.4.2.4.5 Error Detect and Recovery when CQ is enabled
    4. 12.4  Industrial and Control Interfaces
      1. 12.4.1 Enhanced Capture (ECAP) Module
        1. 12.4.1.1 ECAP Overview
          1. 12.4.1.1.1 ECAP Features
          2. 12.4.1.1.2 ECAP Ports
        2. 12.4.1.2 ECAP Environment
        3. 12.4.1.3 ECAP Functional Description
          1. 12.4.1.3.1 Capture and APWM Operating Modes
            1. 12.4.1.3.1.1 ECAP Capture Mode Description
              1. 12.4.1.3.1.1.1 ECAP Event Prescaler
              2. 12.4.1.3.1.1.2 ECAP Edge Polarity Select and Qualifier
              3. 12.4.1.3.1.1.3 ECAP Continuous/One-Shot Control
              4. 12.4.1.3.1.1.4 ECAP 32-Bit Counter and Phase Control
              5. 12.4.1.3.1.1.5 CAP1-CAP4 Registers
              6. 12.4.1.3.1.1.6 ECAP Interrupt Control
              7. 12.4.1.3.1.1.7 ECAP Shadow Load and Lockout Control
            2. 12.4.1.3.1.2 ECAP APWM Mode Operation
          2. 12.4.1.3.2 Summary of ECAP Functional Registers
        4. 12.4.1.4 ECAP Use Cases
          1. 12.4.1.4.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
            1. 12.4.1.4.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
          2. 12.4.1.4.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.4.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
          3. 12.4.1.4.3 Time Difference (Delta) Operation Rising Edge Trigger Example
            1. 12.4.1.4.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
          4. 12.4.1.4.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.4.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
          5. 12.4.1.4.5 Application of the APWM Mode
            1. 12.4.1.4.5.1 Simple PWM Generation (Independent Channel/s) Example
              1. 12.4.1.4.5.1.1 Code Snippet for APWM Mode
            2. 12.4.1.4.5.2 Multichannel PWM Generation with Synchronization Example
              1. 12.4.1.4.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
            3. 12.4.1.4.5.3 Multichannel PWM Generation with Phase Control Example
              1. 12.4.1.4.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
      2. 12.4.2 Enhanced Pulse Width Modulation (EPWM) Module
        1. 12.4.2.1 EPWM Overview
          1. 12.4.2.1.1 EPWM Features
          2. 12.4.2.1.2 EPWM Ports
        2. 12.4.2.2 ECAP Environment
        3. 12.4.2.3 EPWM Functional Description
          1. 12.4.2.3.1  EPWM Submodule Features
            1. 12.4.2.3.1.1 Constant Definitions Used in the EPWM Code Examples
          2. 12.4.2.3.2  EPWM Time-Base (TB) Submodule
            1. 12.4.2.3.2.1 Overview
            2. 12.4.2.3.2.2 Controlling and Monitoring the EPWM Time-Base Submodule
            3. 12.4.2.3.2.3 Calculating PWM Period and Frequency
              1. 12.4.2.3.2.3.1 EPWM Time-Base Period Shadow Register
              2. 12.4.2.3.2.3.2 EPWM Time-Base Counter Synchronization
            4. 12.4.2.3.2.4 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
            5. 12.4.2.3.2.5 EPWM Time-Base Counter Modes and Timing Waveforms
          3. 12.4.2.3.3  EPWM Counter-Compare (CC) Submodule
            1. 12.4.2.3.3.1 Overview
            2. 12.4.2.3.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
            3. 12.4.2.3.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
            4. 12.4.2.3.3.4 EPWM Counter-Compare Submodule Timing Waveforms
          4. 12.4.2.3.4  EPWM Action-Qualifier (AQ) Submodule
            1. 12.4.2.3.4.1 Overview
            2. 12.4.2.3.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
            3. 12.4.2.3.4.3 EPWM Action-Qualifier Event Priority
            4. 12.4.2.3.4.4 Waveforms for Common EPWM Configurations
          5. 12.4.2.3.5  EPWM Dead-Band Generator (DB) Submodule
            1. 12.4.2.3.5.1 Overview
            2. 12.4.2.3.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
            3. 12.4.2.3.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
          6. 12.4.2.3.6  EPWM-Chopper (PC) Submodule
            1. 12.4.2.3.6.1 Overview
            2. 12.4.2.3.6.2 2594
            3. 12.4.2.3.6.3 Controlling the EPWM-Chopper Submodule
            4. 12.4.2.3.6.4 Operational Highlights for the EPWM-Chopper Submodule
            5. 12.4.2.3.6.5 EPWM-Chopper Waveforms
              1. 12.4.2.3.6.5.1 EPWM-Chopper One-Shot Pulse
              2. 12.4.2.3.6.5.2 EPWM-Chopper Duty Cycle Control
          7. 12.4.2.3.7  EPWM Trip-Zone (TZ) Submodule
            1. 12.4.2.3.7.1 Overview
            2. 12.4.2.3.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
            3. 12.4.2.3.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
            4. 12.4.2.3.7.4 Generating EPWM Trip-Event Interrupts
          8. 12.4.2.3.8  EPWM Event-Trigger (ET) Submodule
            1. 12.4.2.3.8.1 Overview
            2. 12.4.2.3.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
            3. 12.4.2.3.8.3 Operational Overview of the EPWM Event-Trigger Submodule
            4. 12.4.2.3.8.4 2609
          9. 12.4.2.3.9  EPWM High Resolution (HRPWM) Submodule
            1. 12.4.2.3.9.1 Overview
            2. 12.4.2.3.9.2 Architecture of the High-Resolution PWM Submodule
            3. 12.4.2.3.9.3 Controlling and Monitoring the High-Resolution PWM Submodule
            4. 12.4.2.3.9.4 Configuring the High-Resolution PWM Submodule
            5. 12.4.2.3.9.5 Operational Highlights for the High-Resolution PWM Submodule
              1. 12.4.2.3.9.5.1 HRPWM Edge Positioning
              2. 12.4.2.3.9.5.2 HRPWM Scaling Considerations
              3. 12.4.2.3.9.5.3 HRPWM Duty Cycle Range Limitation
          10. 12.4.2.3.10 EPWM / HRPWM Functional Register Groups
          11. 12.4.2.3.11 Proper EPWM Interrupt Initialization Procedure
      3. 12.4.3 Enhanced Quadrature Encoder Pulse (EQEP) Module
        1. 12.4.3.1 EQEP Overview
          1. 12.4.3.1.1 EQEP Features
          2. 12.4.3.1.2 EQEP Ports
        2. 12.4.3.2 EQEP Environment
        3. 12.4.3.3 EQEP Functional Description
          1. 12.4.3.3.1 EQEP Inputs
          2. 12.4.3.3.2 EQEP Quadrature Decoder Unit (QDU)
            1. 12.4.3.3.2.1 EQEP Position Counter Input Modes
              1. 12.4.3.3.2.1.1 Quadrature Count Mode
              2. 12.4.3.3.2.1.2 EQEP Direction-count Mode
              3. 12.4.3.3.2.1.3 EQEP Up-Count Mode
              4. 12.4.3.3.2.1.4 EQEP Down-Count Mode
            2. 12.4.3.3.2.2 EQEP Input Polarity Selection
            3. 12.4.3.3.2.3 EQEP Position-Compare Sync Output
          3. 12.4.3.3.3 EQEP Position Counter and Control Unit (PCCU)
            1. 12.4.3.3.3.1 EQEP Position Counter Operating Modes
              1. 12.4.3.3.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
              2. 12.4.3.3.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
              3. 12.4.3.3.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
              4. 12.4.3.3.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
            2. 12.4.3.3.3.2 EQEP Position Counter Latch
              1. 12.4.3.3.3.2.1 Index Event Latch
              2. 12.4.3.3.3.2.2 EQEP Strobe Event Latch
            3. 12.4.3.3.3.3 EQEP Position Counter Initialization
            4. 12.4.3.3.3.4 EQEP Position-Compare Unit
          4. 12.4.3.3.4 EQEP Edge Capture Unit
          5. 12.4.3.3.5 EQEP Watchdog
          6. 12.4.3.3.6 Unit Timer Base
          7. 12.4.3.3.7 EQEP Interrupt Structure
          8. 12.4.3.3.8 Summary of EQEP Functional Registers
      4. 12.4.4 Controller Area Network (MCAN)
        1. 12.4.4.1 MCAN Overview
          1. 12.4.4.1.1 MCAN Features
          2. 12.4.4.1.2 MCAN Ports
        2. 12.4.4.2 MCAN Environment
        3. 12.4.4.3 MCAN Functional Description
          1. 12.4.4.3.1  Module Clocking Requirements
          2. 12.4.4.3.2  Interrupt and DMA Requests
            1. 12.4.4.3.2.1 Interrupt Requests
            2. 12.4.4.3.2.2 DMA Requests
          3. 12.4.4.3.3  Operating Modes
            1. 12.4.4.3.3.1 Software Initialization
            2. 12.4.4.3.3.2 Normal Operation
            3. 12.4.4.3.3.3 CAN FD Operation
            4. 12.4.4.3.3.4 Transmitter Delay Compensation
              1. 12.4.4.3.3.4.1 Description
              2. 12.4.4.3.3.4.2 Transmitter Delay Compensation Measurement
            5. 12.4.4.3.3.5 Restricted Operation Mode
            6. 12.4.4.3.3.6 Bus Monitoring Mode
            7. 12.4.4.3.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 12.4.4.3.3.7.1 Frame Transmission in DAR Mode
            8. 12.4.4.3.3.8 Power Down (Sleep Mode)
              1. 12.4.4.3.3.8.1 External Clock Stop Mode
              2. 12.4.4.3.3.8.2 Suspend Mode
              3. 12.4.4.3.3.8.3 Wakeup request
            9. 12.4.4.3.3.9 Test Modes
              1. 12.4.4.3.3.9.1 Internal Loopback Mode
          4. 12.4.4.3.4  Timestamp Generation
            1. 12.4.4.3.4.1 External Timestamp Counter
          5. 12.4.4.3.5  Timeout Counter
          6. 12.4.4.3.6  ECC Support
            1. 12.4.4.3.6.1 ECC Wrapper
            2. 12.4.4.3.6.2 ECC Aggregator
          7. 12.4.4.3.7  Rx Handling
            1. 12.4.4.3.7.1 Acceptance Filtering
              1. 12.4.4.3.7.1.1 Range Filter
              2. 12.4.4.3.7.1.2 Filter for specific IDs
              3. 12.4.4.3.7.1.3 Classic Bit Mask Filter
              4. 12.4.4.3.7.1.4 Standard Message ID Filtering
              5. 12.4.4.3.7.1.5 Extended Message ID Filtering
            2. 12.4.4.3.7.2 Rx FIFOs
              1. 12.4.4.3.7.2.1 Rx FIFO Blocking Mode
              2. 12.4.4.3.7.2.2 Rx FIFO Overwrite Mode
            3. 12.4.4.3.7.3 Dedicated Rx Buffers
              1. 12.4.4.3.7.3.1 Rx Buffer Handling
            4. 12.4.4.3.7.4 Debug on CAN Support
          8. 12.4.4.3.8  Tx Handling
            1. 12.4.4.3.8.1 Transmit Pause
            2. 12.4.4.3.8.2 Dedicated Tx Buffers
            3. 12.4.4.3.8.3 Tx FIFO
            4. 12.4.4.3.8.4 Tx Queue
            5. 12.4.4.3.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 12.4.4.3.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 12.4.4.3.8.7 Transmit Cancellation
            8. 12.4.4.3.8.8 Tx Event Handling
          9. 12.4.4.3.9  FIFO Acknowledge Handling
          10. 12.4.4.3.10 Message RAM
            1. 12.4.4.3.10.1 Message RAM Configuration
            2. 12.4.4.3.10.2 Rx Buffer and FIFO Element
            3. 12.4.4.3.10.3 Tx Buffer Element
            4. 12.4.4.3.10.4 Tx Event FIFO Element
            5. 12.4.4.3.10.5 Standard Message ID Filter Element
            6. 12.4.4.3.10.6 Extended Message ID Filter Element
    5. 12.5  Audio Interfaces
      1. 12.5.1 Audio Tracking Logic (ATL)
        1. 12.5.1.1 ATL Overview
          1. 12.5.1.1.1 ATL Features Overview
          2. 12.5.1.1.2 ATL Ports
      2. 12.5.2 Multichannel Audio Serial Port (MCASP)
        1. 12.5.2.1 MCASP Overview
          1. 12.5.2.1.1 MCASP Features
          2. 12.5.2.1.2 MCASP Ports
        2. 12.5.2.2 MCASP Environment
        3. 12.5.2.3 MCASP Functional Description
          1. 12.5.2.3.1  MCASP Block Diagram
          2. 12.5.2.3.2  MCASP Clock and Frame-Sync Configurations
            1. 12.5.2.3.2.1 MCASP Transmit Clock
            2. 12.5.2.3.2.2 MCASP Receive Clock
            3. 12.5.2.3.2.3 Frame-Sync Generator
            4. 12.5.2.3.2.4 Synchronous and Asynchronous Transmit and Receive Operations
          3. 12.5.2.3.3  MCASP Frame Sync Feedback for Cross Synchronization
          4. 12.5.2.3.4  MCASP Serializers
          5. 12.5.2.3.5  MCASP Format Units
            1. 12.5.2.3.5.1 Transmit Format Unit
              1. 12.5.2.3.5.1.1 TDM Mode Transmission Data Alignment Settings
              2. 12.5.2.3.5.1.2 DIT Mode Transmission Data Alignment Settings
            2. 12.5.2.3.5.2 Receive Format Unit
              1. 12.5.2.3.5.2.1 TDM Mode Reception Data Alignment Settings
          6. 12.5.2.3.6  MCASP State-Machines
          7. 12.5.2.3.7  MCASP TDM Sequencers
          8. 12.5.2.3.8  MCASP Software Reset
          9. 12.5.2.3.9  MCASP Power Management
          10. 12.5.2.3.10 MCASP Transfer Modes
            1. 12.5.2.3.10.1 Burst Transfer Mode
            2. 12.5.2.3.10.2 Time-Division Multiplexed (TDM) Transfer Mode
              1. 12.5.2.3.10.2.1 TDM Time Slots Generation and Processing
              2. 12.5.2.3.10.2.2 Special 384-Slot TDM Mode for Connection to External DIR
            3. 12.5.2.3.10.3 DIT Transfer Mode
              1. 12.5.2.3.10.3.1 Transmit DIT Encoding
              2. 12.5.2.3.10.3.2 Transmit DIT Clock and Frame-Sync Generation
              3. 12.5.2.3.10.3.3 DIT Channel Status and User Data Register Files
          11. 12.5.2.3.11 MCASP Data Transmission and Reception
            1. 12.5.2.3.11.1 Data Ready Status and Event/Interrupt Generation
              1. 12.5.2.3.11.1.1 Transmit Data Ready
              2. 12.5.2.3.11.1.2 Receive Data Ready
              3. 12.5.2.3.11.1.3 Transfers Through the Data Port (DATA)
              4. 12.5.2.3.11.1.4 Transfers Through the Configuration Bus (CFG)
              5. 12.5.2.3.11.1.5 Using a Device CPU for MCASP Servicing
              6. 12.5.2.3.11.1.6 Using the DMA for MCASP Servicing
          12. 12.5.2.3.12 MCASP Audio FIFO (AFIFO)
            1. 12.5.2.3.12.1 AFIFO Data Transmission
              1. 12.5.2.3.12.1.1 Transmit DMA Event Pacer
            2. 12.5.2.3.12.2 AFIFO Data Reception
              1. 12.5.2.3.12.2.1 Receive DMA Event Pacer
            3. 12.5.2.3.12.3 Arbitration Between Transmit and Receive DMA Requests
          13. 12.5.2.3.13 MCASP Events and Interrupt Requests
            1. 12.5.2.3.13.1 Transmit Data Ready Event and Interrupt
            2. 12.5.2.3.13.2 Receive Data Ready Event and Interrupt
            3. 12.5.2.3.13.3 Error Interrupt
            4. 12.5.2.3.13.4 Multiple Interrupts
          14. 12.5.2.3.14 MCASP DMA Requests
          15. 12.5.2.3.15 MCASP Loopback Modes
            1. 12.5.2.3.15.1 Loopback Mode Configurations
          16. 12.5.2.3.16 MCASP Error Reporting
            1. 12.5.2.3.16.1 Buffer Underrun Error -Transmitter
            2. 12.5.2.3.16.2 Buffer Overrun Error-Receiver
            3. 12.5.2.3.16.3 DATA Port Error - Transmitter
            4. 12.5.2.3.16.4 DATA Port Error - Receiver
            5. 12.5.2.3.16.5 Unexpected Frame Sync Error
            6. 12.5.2.3.16.6 Clock Failure Detection
              1. 12.5.2.3.16.6.1 Clock Failure Check Startup
              2. 12.5.2.3.16.6.2 Transmit Clock Failure Check and Recovery
              3. 12.5.2.3.16.6.3 Receive Clock Failure Check and Recovery
        4. 12.5.2.4 MCASP Programming Guide
          1. 12.5.2.4.1 MCASP Operational Modes Configuration
            1. 12.5.2.4.1.1 MCASP Transmission Modes
              1. 12.5.2.4.1.1.1 Main Sequence – MCASP DIT- /TDM- Polling Transmission Method
              2. 12.5.2.4.1.1.2 Main Sequence – MCASP DIT- /TDM - Interrupt Transmission Method
              3. 12.5.2.4.1.1.3 Main Sequence –MCASP DIT- /TDM - Mode DMA Transmission Method
            2. 12.5.2.4.1.2 MCASP Reception Modes
              1. 12.5.2.4.1.2.1 Main Sequence – MCASP Polling Reception Method
              2. 12.5.2.4.1.2.2 Main Sequence – MCASP TDM - Interrupt Reception Method
              3. 12.5.2.4.1.2.3 Main Sequence – MCASP TDM - Mode DMA Reception Method
            3. 12.5.2.4.1.3 MCASP Event Servicing
              1. 12.5.2.4.1.3.1 MCASP DIT-/TDM- Transmit Interrupt Events Servicing
              2. 12.5.2.4.1.3.2 MCASP TDM- Receive Interrupt Events Servicing
              3. 12.5.2.4.1.3.3 Subsequence – MCASP DIT-/TDM -Modes Transmit Error Handling
              4. 12.5.2.4.1.3.4 Subsequence – MCASP Receive Error Handling
    6. 12.6  Display Subsystem (DSS) and Peripherals
      1. 12.6.1 DSS Overview
        1. 12.6.1.1 DSS Features
        2. 12.6.1.2 DSS Ports
      2. 12.6.2 DSS Environment
      3. 12.6.3 Display Subsystem Controller (DISPC) with Frame Buffer Decompression Core (FBDC)
        1. 12.6.3.1  DISPC Overview
        2. 12.6.3.2  DISPC Clocks
        3. 12.6.3.3  DISPC Resets
        4. 12.6.3.4  DISPC Power Management
        5. 12.6.3.5  DISPC Interrupt Requests
        6. 12.6.3.6  DISPC DMA Controller
          1. 12.6.3.6.1  DISPC DMA Addressing and Bursts
          2. 12.6.3.6.2  DISPC Read DMA Buffers
          3. 12.6.3.6.3  DISPC Write DMA Buffer
          4. 12.6.3.6.4  DISPC Flip/Mirror Support
          5. 12.6.3.6.5  DISPC DMA Predecimation
          6. 12.6.3.6.6  DISPC DMA Buffer Sharing
          7. 12.6.3.6.7  DISPC DMA MFLAG Mechanism
          8. 12.6.3.6.8  DISPC DMA Priority Requests Control
          9. 12.6.3.6.9  DISPC DMA Arbitration
          10. 12.6.3.6.10 DISPC DMA Ultra-Low Power Mode
          11. 12.6.3.6.11 DISPC Compressed Data Format Support
            1. 12.6.3.6.11.1 FBDC Tile Request
            2. 12.6.3.6.11.2 FBDC Source Cropping
        7. 12.6.3.7  DISPC Pixel Data Formats
        8. 12.6.3.8  DISPC Video Pipeline
          1. 12.6.3.8.1 DISPC VID Replication Logic
          2. 12.6.3.8.2 DISPC VID VC-1 Range Mapping Unit
          3. 12.6.3.8.3 DISPC VID Color Look-Up Table (CLUT)
          4. 12.6.3.8.4 DISPC VID Chrominance Resampling
            1. 12.6.3.8.4.1 Chrominance Resampling for VID Pipeline
            2. 12.6.3.8.4.2 Chrominance Resampling for VIDL Pipeline
          5. 12.6.3.8.5 DISPC VID Scaler Unit
          6. 12.6.3.8.6 DISPC VID Color Space Conversion YUV to RGB
          7. 12.6.3.8.7 DISPC VID Brightness/Contrast/Saturation/Hue Control
          8. 12.6.3.8.8 DISPC VID Luma Key Support
          9. 12.6.3.8.9 DISPC VID Cropping Support
        9. 12.6.3.9  DISPC Write-Back Pipeline
          1. 12.6.3.9.1 DISPC WB Color Space Conversion RGB to YUV
          2. 12.6.3.9.2 DISPC WB Scaler Unit
        10. 12.6.3.10 DISPC Overlay Manager
          1. 12.6.3.10.1 DISPC Overlay Input Selector
          2. 12.6.3.10.2 DISPC Overlay Mechanism
            1. 12.6.3.10.2.1 Overlay Alpha Blender
            2. 12.6.3.10.2.2 Overlay Transparency Color Keys
          3. 12.6.3.10.3 Overlay 3D Support
          4. 12.6.3.10.4 Overlay Color Bar Insertion
        11. 12.6.3.11 DISPC Video Port Output
          1. 12.6.3.11.1 DISPC VP Gamma Correction Unit
          2. 12.6.3.11.2 DISPC VP Color Phase Rotation Unit
          3. 12.6.3.11.3 DISPC VP Color Space Conversion - RGB to YUV
          4. 12.6.3.11.4 DISPC VP BT.656 and BT.1120 Modes
            1. 12.6.3.11.4.1 DISPC BT Mode Blanking
            2. 12.6.3.11.4.2 DISPC BT Mode EAV and SAV
          5. 12.6.3.11.5 DISPC VP Spatial/Temporal Dithering
          6. 12.6.3.11.6 DISPC VP Multiple Cycle Output Format (TDM)
          7. 12.6.3.11.7 DISPC VP Stall Mode
          8. 12.6.3.11.8 DISPC VP Timing Generator and Display Panel Settings
          9. 12.6.3.11.9 DISPC VP Merge-Split-Sync (MSS) Module
            1. 12.6.3.11.9.1 MSS Clocking Scheme
            2. 12.6.3.11.9.2 MSS Merge with Scaling
        12. 12.6.3.12 DISPC Internal Diagnostic Features
          1. 12.6.3.12.1 Internal Diagnostic Check Regions
          2. 12.6.3.12.2 Internal Diagnostic Signature Generator Using MISR
          3. 12.6.3.12.3 Internal Diagnostic Checks
          4. 12.6.3.12.4 Internal Diagnostic Check Limitations
        13. 12.6.3.13 DISPC Security Management
          1. 12.6.3.13.1 Security Implementation
          2. 12.6.3.13.2 Secure Mode Configuration
        14. 12.6.3.14 DISPC Resources Sharing
          1. 12.6.3.14.1 Register Region per Sub-component
          2. 12.6.3.14.2 Interrupt Duplication
          3. 12.6.3.14.3 Independent Context Update for Pipelines
          4. 12.6.3.14.4 CHANNELID Support
        15. 12.6.3.15 DISPC Shadow Mechanism for Registers
      4. 12.6.4 MIPI Display Serial Interface (DSI) Controller
        1. 12.6.4.1 DSI Block Diagram
        2. 12.6.4.2 DSI Clocking
        3. 12.6.4.3 DSI Reset
        4. 12.6.4.4 DSI Power Management
        5. 12.6.4.5 DSI Interrupts
        6. 12.6.4.6 DSI Internal Interfaces
          1. 12.6.4.6.1 Video Input Interfaces
            1. 12.6.4.6.1.1 Pixel Mapping
          2. 12.6.4.6.2 DPI (Pixel Stream Interface)
            1. 12.6.4.6.2.1 Signals
          3. 12.6.4.6.3 SDI (Serial Data Interface)
            1. 12.6.4.6.3.1 Secure Display Support
        7. 12.6.4.7 DSI Programming Guide
          1. 12.6.4.7.1  Application Guidelines
            1. 12.6.4.7.1.1 Overview of a Display Subsystem
            2. 12.6.4.7.1.2 D-PHY And DSI Configuration
            3. 12.6.4.7.1.3 DSI Controller Initialization
            4. 12.6.4.7.1.4 Panel Configuration Using Command Mode
            5. 12.6.4.7.1.5 VIDEO Interface Configuration
          2. 12.6.4.7.2  Application Considerations
            1. 12.6.4.7.2.1 D-PHY Timings Control
            2. 12.6.4.7.2.2 Control Block
            3. 12.6.4.7.2.3 Video Coherency
          3. 12.6.4.7.3  Start-up Procedure
          4. 12.6.4.7.4  Interrupt Management
            1. 12.6.4.7.4.1 Error and Status Registers
            2. 12.6.4.7.4.2 Interrupt Management for Direct Command Registers
          5. 12.6.4.7.5  Direct Command Usage
            1. 12.6.4.7.5.1 Trigger Mapping Information
            2. 12.6.4.7.5.2 Command Mode Settings
            3. 12.6.4.7.5.3 Bus Turnaround Sequence
            4. 12.6.4.7.5.4 Tearing Effect Control
            5. 12.6.4.7.5.5 Tearing Effect Control on Panels with Frame Buffer
            6. 12.6.4.7.5.6 Return Path Operation
            7. 12.6.4.7.5.7 EoT Packet Management
            8. 12.6.4.7.5.8 ECC Correction
            9. 12.6.4.7.5.9 LP Transmission and BTA
          6. 12.6.4.7.6  Low-power Management
          7. 12.6.4.7.7  Video Mode Settings
            1. 12.6.4.7.7.1 Video Stream Presentation
            2. 12.6.4.7.7.2 Video Stream Settings (VSG)
            3. 12.6.4.7.7.3 VCA Configuration
            4. 12.6.4.7.7.4 TVG Configuration
          8. 12.6.4.7.8  DPI To DSI Programming
            1. 12.6.4.7.8.1 DSI and DPHY Operation
            2. 12.6.4.7.8.2 Pixel Clock to TX_BYTE_CLK Variation
            3. 12.6.4.7.8.3 LP Operation
            4. 12.6.4.7.8.4 DPI Interface Burst Operation
          9. 12.6.4.7.9  Programming the DSITX Controller to Match the Incoming DPI Stream
            1. 12.6.4.7.9.1 Vertical Timing
            2. 12.6.4.7.9.2 Horizontal Timing for Non-Burst Mode with Sync Pulses
            3. 12.6.4.7.9.3 Event Mode Horizontal Timing
            4. 12.6.4.7.9.4 Burst Event Mode Horizontal Timing
            5. 12.6.4.7.9.5 Burst Mode Operation
            6. 12.6.4.7.9.6 Example Configurations
            7. 12.6.4.7.9.7 Stereoscopic Video Support
          10. 12.6.4.7.10 DSITX Video Stream Variable Refresh
      5. 12.6.5 Embedded DisplayPort (еDP) Transmitter
        1. 12.6.5.1 EDP Block Diagram
        2. 12.6.5.2 EDP Wrapper Functions
          1. 12.6.5.2.1 Video Stream Clock/Data Muxing
          2. 12.6.5.2.2 Secure Video Content Protection
          3. 12.6.5.2.3 DPI_DATA Input Pixel Format Supported
          4. 12.6.5.2.4 Audio Input Interface
            1. 12.6.5.2.4.1 Audio I2S Signals/Timing
            2. 12.6.5.2.4.2 Audio I2S Clock Frequency
        3. 12.6.5.3 EDP Transmitter Controller Subsystem (MHDPTX_TOP)
          1. 12.6.5.3.1 Display Stream Compression Encoder (DSC)
            1. 12.6.5.3.1.1 DSC Encoder Features
            2. 12.6.5.3.1.2 Usage Models for EDP
          2. 12.6.5.3.2 Display Port Transmitter Controller (MHDPTX Controller)
            1. 12.6.5.3.2.1 EDP Transmitter Controller Mode Configurations
        4. 12.6.5.4 EDP AUX_PHY Interface
        5. 12.6.5.5 EDP Clocks
          1. 12.6.5.5.1 Clock Diagram
            1. 12.6.5.5.1.1 DPI Interface Clock Sourcing
            2. 12.6.5.5.1.2 Memory Clock Gating
            3. 12.6.5.5.1.3 PHY Clock Connections
          2. 12.6.5.5.2 Clock Groups
        6. 12.6.5.6 EDP Resets
        7. 12.6.5.7 EDP Interrupt Requests
          1. 12.6.5.7.1 EDP_INTR Interrupt Description
          2. 12.6.5.7.2 EDP_INTR_ASF Interrupt Description
        8. 12.6.5.8 EDP Embedded Memories
          1. 12.6.5.8.1 MHDPTX Controller Memories
          2. 12.6.5.8.2 DSC Memories
          3. 12.6.5.8.3 ECC Aggregation
        9. 12.6.5.9 EDP Programmer's Guide
          1. 12.6.5.9.1 EDP Controller Programming
            1. 12.6.5.9.1.1  MHDPTX Register/Memory Regions
            2. 12.6.5.9.1.2  Boot Sequence
            3. 12.6.5.9.1.3  Setting Core Clock Frequency
            4. 12.6.5.9.1.4  Loading Firmware
            5. 12.6.5.9.1.5  FW Running indication
            6. 12.6.5.9.1.6  Software Events Handling
            7. 12.6.5.9.1.7  DisplayPort Source (TX) Sequence
            8. 12.6.5.9.1.8  HDCP
              1. 12.6.5.9.1.8.1 Embedded HDCP Crypto
              2. 12.6.5.9.1.8.2 Additional Security Features
                1. 12.6.5.9.1.8.2.1 KM-Key Encryption
                2. 12.6.5.9.1.8.2.2 Cyphertext Stealing
            9. 12.6.5.9.1.9  HD Display TX Controller
              1. 12.6.5.9.1.9.1 Info-Frame Handling
                1. 12.6.5.9.1.9.1.1 EDID Handling
                2. 12.6.5.9.1.9.1.2 Audio Control
                3. 12.6.5.9.1.9.1.3 Video Control
            10. 12.6.5.9.1.10 DPTX TX Controller
              1. 12.6.5.9.1.10.1 Protocol over Auxiliary
              2. 12.6.5.9.1.10.2 PHY (Physical layer) Handling
          2. 12.6.5.9.2 EDP PHY Wrapper Initialization
          3. 12.6.5.9.3 EDP PHY Programming
    7. 12.7  Camera Subsystem
      1. 12.7.1 Camera Streaming Interface Receiver (CSI_RX_IF)
        1. 12.7.1.1 CSI_RX_IF Overview
          1. 12.7.1.1.1 CSI_RX_IF Features
          2. 12.7.1.1.2 CSI_RX_IF Ports
        2. 12.7.1.2 CSI_RX_IF Environment
        3. 12.7.1.3 CSI_RX_IF Functional Description
          1. 12.7.1.3.1 CSI_RX_IF Block Diagram
          2. 12.7.1.3.2 CSI_RX_IF Hardware and Software Reset
          3. 12.7.1.3.3 CSI_RX_IF Clock Configuration
          4. 12.7.1.3.4 CSI_RX_IF Interrupt Events
          5. 12.7.1.3.5 CSI_RX_IF Data Memory Organization Details
          6. 12.7.1.3.6 CSI_RX_IF PSI_L (DMA) Interface
            1. 12.7.1.3.6.1 PSI_L DMA framing
            2. 12.7.1.3.6.2 PSI_L DMA error handling due to FIFO overflow
          7. 12.7.1.3.7 CSI_RX_IF ECC Protection Support
          8. 12.7.1.3.8 CSI_RX_IF Programming Guide
            1. 12.7.1.3.8.1  Overview
            2. 12.7.1.3.8.2  Controller Configuration
            3. 12.7.1.3.8.3  Power on Configuration
            4. 12.7.1.3.8.4  Stream Start and Stop
            5. 12.7.1.3.8.5  Error Control With Soft Resets
            6. 12.7.1.3.8.6  Stream Error Detected – No Error Bypass Mode
            7. 12.7.1.3.8.7  Stream Error Detected – Error Bypass Mode
            8. 12.7.1.3.8.8  Stream Error Detected – Soft Reset Recovery
            9. 12.7.1.3.8.9  Stream Monitor Configuration
            10. 12.7.1.3.8.10 Stream Monitor Frame Capture Control
            11. 12.7.1.3.8.11 Stream Monitor Timer interrupt
            12. 12.7.1.3.8.12 Stream Monitor Line/Byte Counters Interrupt
            13. 12.7.1.3.8.13 Example Controller Programming Sequence (Single Stream Operation)
            14. 12.7.1.3.8.14 CSI_RX_IF Programming Restrictions
            15. 12.7.1.3.8.15 CSI_RX_IF Real-time operating requirements
      2. 12.7.2 MIPI D-PHY Receiver (DPHY_RX)
        1. 12.7.2.1 DPHY_RX Overview
          1. 12.7.2.1.1 DPHY_RX Features
          2. 12.7.2.1.2 DPHY_RX Ports
        2. 12.7.2.2 DPHY_RX Environment
        3. 12.7.2.3 DPHY_RX Functional Description
          1. 12.7.2.3.1 DPHY_RX Programming Guide
            1. 12.7.2.3.1.1 Overview
            2. 12.7.2.3.1.2 Initial Configuration Programming
              1. 12.7.2.3.1.2.1 Start-up Sequence Timing Diagram
            3. 12.7.2.3.1.3 Common Configuration
            4. 12.7.2.3.1.4 Lane Configuration
            5. 12.7.2.3.1.5 Procedure: Clock Lane Low Power Analog Receiver Functions Test
              1. 12.7.2.3.1.5.1 Description of Procedure
              2. 12.7.2.3.1.5.2 Details of the Procedure
            6. 12.7.2.3.1.6 Procedure: Data Lane Low Power Analog Receiver Functions Test
              1. 12.7.2.3.1.6.1 Description of Procedure
              2. 12.7.2.3.1.6.2 Details of the Procedure
            7. 12.7.2.3.1.7 Procedure: Clock and Data Lane High Speed Receiver BIST Functions Test
              1. 12.7.2.3.1.7.1 Description of Procedure
              2. 12.7.2.3.1.7.2 Details of the Procedure
      3. 12.7.3 Camera Streaming Interface Transmitter (CSI_TX_IF)
        1. 12.7.3.1 CSI_TX_IF Overview
          1. 12.7.3.1.1 CSI_TX_IF Ports
        2. 12.7.3.2 CSI_TX_IF Features
          1. 12.7.3.2.1 CSI_TX_IF Legacy Compatibility
        3. 12.7.3.3 CSI_TX_IF Environment
        4. 12.7.3.4 CSI_TX_IF Functional Description
          1. 12.7.3.4.1 CSI_TX_IF Block Diagram
          2. 12.7.3.4.2 CSI_TX_IF Hardware and Software Reset
          3. 12.7.3.4.3 CSI_TX_IF Clock Configuration
          4. 12.7.3.4.4 CSI_TX_IF Interrupt Events
          5. 12.7.3.4.5 CSI_TX_IF Data Memory Organization Details
          6. 12.7.3.4.6 CSI_TX_IF PSI_L (DMA) Interface
          7. 12.7.3.4.7 CSI_TX_IF ECC Protection Support
        5. 12.7.3.5 CSI_TX_IF Programming Guide
          1. 12.7.3.5.1  CSI_TX_IF Programming (Configuration Mode)
          2. 12.7.3.5.2  CSI_TX_IF System Initialization Programming
          3. 12.7.3.5.3  CSI_TX_IF Lane Control Programming
          4. 12.7.3.5.4  CSI_TX_IF Virtual Channel and Data Type Management
            1. 12.7.3.5.4.1 CSI_TX_IF Data Type Interleaving
            2. 12.7.3.5.4.2 CSI_TX_IF Data Type Interleaving with Multiple Interfaces
            3. 12.7.3.5.4.3 CSI_TX_IF Virtual Channel Interleaving
            4. 12.7.3.5.4.4 CSI_TX_IF Virtual Channel and Data Type Interleaving
          5. 12.7.3.5.5  CSI_TX_IF Line Control
            1. 12.7.3.5.5.1 CSI_TX_IF Line Control Arbitration
          6. 12.7.3.5.6  CSI_TX_IF Lane Manager FSM
          7. 12.7.3.5.7  CSI_TX_IF Data Lane Control FSM
          8. 12.7.3.5.8  CSI_TX_IF Application Examples
            1. 12.7.3.5.8.1 CSI_TX_IF D-PHY Control and Configuration
            2. 12.7.3.5.8.2 CSI_TX_IF Clock and Data Lane Enable
            3. 12.7.3.5.8.3 CSI_TX_IF DP/DN Signal Swap
          9. 12.7.3.5.9  CSI_TX_IF DPHY_TX Status
          10. 12.7.3.5.10 CSI_TX_IF ULPS Operation
          11. 12.7.3.5.11 CSI_TX_IF System Frame Rate Measurement
          12. 12.7.3.5.12 CSI_TX_IF Configuration for PSI_L
          13. 12.7.3.5.13 CSI_TX_IF Configuration for Color Bar
          14. 12.7.3.5.14 CSI_TX_IF Error Recovery
          15. 12.7.3.5.15 CSI_TX_IF Power up/down Sequence
    8. 12.8  Shared MIPI D-PHY Transmitter (DPHY_TX)
      1. 12.8.1 DPHY_TX Subsystem Overview
        1. 12.8.1.1 DPHY_TX Features
        2. 12.8.1.2 DPHY_TX Ports
      2. 12.8.2 DPHY_TX Environment
    9. 12.9  Timer Modules
      1. 12.9.1 Global Timebase Counter (GTC)
        1. 12.9.1.1 GTC Overview
          1. 12.9.1.1.1 GTC Features
          2. 12.9.1.1.2 GTC Ports
        2. 12.9.1.2 GTC Functional Description
          1. 12.9.1.2.1 GTC Block Diagram
          2. 12.9.1.2.2 GTC Counter
          3. 12.9.1.2.3 GTC Gray Encoder
          4. 12.9.1.2.4 GTC Push Event Generation
          5. 12.9.1.2.5 GTC Register Partitioning
      2. 12.9.2 Windowed Watchdog Timer (WWDT)
        1. 12.9.2.1 RTI Overview
          1. 12.9.2.1.1 RTI Features
          2. 12.9.2.1.2 RTI Not Supported Features
          3. 12.9.2.1.3 RTI Ports
        2. 12.9.2.2 RTI Functional Description
          1. 12.9.2.2.1 RTI Counter Operation
          2. 12.9.2.2.2 RTI Digital Watchdog
          3. 12.9.2.2.3 RTI Digital Windowed Watchdog
          4. 12.9.2.2.4 RTI Low Power Mode Operation
          5. 12.9.2.2.5 RTI Debug Mode Behavior
      3. 12.9.3 Timers
        1. 12.9.3.1 Timers Overview
          1. 12.9.3.1.1 Timers Features
          2. 12.9.3.1.2 Timers Ports
        2. 12.9.3.2 Timers Environment
        3. 12.9.3.3 Timers Functional Description
          1. 12.9.3.3.1  Timer Block Diagram
          2. 12.9.3.3.2  Timer Power Management
            1. 12.9.3.3.2.1 Wake-Up Capability
          3. 12.9.3.3.3  Timer Software Reset
          4. 12.9.3.3.4  Timer Interrupts
          5. 12.9.3.3.5  Timer Mode Functionality
            1. 12.9.3.3.5.1 1-ms Tick Generation
          6. 12.9.3.3.6  Timer Capture Mode Functionality
          7. 12.9.3.3.7  Timer Compare Mode Functionality
          8. 12.9.3.3.8  Timer Prescaler Functionality
          9. 12.9.3.3.9  Timer Pulse-Width Modulation
          10. 12.9.3.3.10 Timer Counting Rate
          11. 12.9.3.3.11 Timer Under Emulation
          12. 12.9.3.3.12 Accessing Timer Registers
            1. 12.9.3.3.12.1 Writing to Timer Registers
              1. 12.9.3.3.12.1.1 Write Posting Synchronization Mode
              2. 12.9.3.3.12.1.2 Write Nonposting Synchronization Mode
            2. 12.9.3.3.12.2 Reading From Timer Counter Registers
              1. 12.9.3.3.12.2.1 Read Posted
              2. 12.9.3.3.12.2.2 Read Non-Posted
          13. 12.9.3.3.13 Timer Posted Mode Selection
        4. 12.9.3.4 Timers Low-Level Programming Models
          1. 12.9.3.4.1 Timer Operational Mode Configuration
            1. 12.9.3.4.1.1 Timer Mode
              1. 12.9.3.4.1.1.1 Main Sequence – Timer Mode Configuration
            2. 12.9.3.4.1.2 Timer Compare Mode
              1. 12.9.3.4.1.2.1 Main Sequence – Timer Compare Mode Configuration
            3. 12.9.3.4.1.3 Timer Capture Mode
              1. 12.9.3.4.1.3.1 Main Sequence – Timer Capture Mode Configuration
              2. 12.9.3.4.1.3.2 Subsequence – Initialize Capture Mode
              3. 12.9.3.4.1.3.3 Subsequence – Detect Event
            4. 12.9.3.4.1.4 Timer PWM Mode
              1. 12.9.3.4.1.4.1 Main Sequence – Timer PWM Mode Configuration
    10. 12.10 Internal Diagnostics Modules
      1. 12.10.1 Dual Clock Comparator (DCC)
        1. 12.10.1.1 DCC Overview
          1. 12.10.1.1.1 DCC Features
          2. 12.10.1.1.2 DCC Ports
        2. 12.10.1.2 DCC Functional Description
          1. 12.10.1.2.1 DCC Counter Operation
          2. 12.10.1.2.2 DCC Low Power Mode Operation
          3. 12.10.1.2.3 DCC Suspend Mode Behavior
          4. 12.10.1.2.4 DCC Single-Shot Mode
          5. 12.10.1.2.5 DCC Continuous mode
            1. 12.10.1.2.5.1 DCC Continue on Error
            2. 12.10.1.2.5.2 DCC Error Count
          6. 12.10.1.2.6 DCC Control and count hand-off across clock domains
          7. 12.10.1.2.7 DCC Error Trajectory record
            1. 12.10.1.2.7.1 DCC FIFO capturing for Errors
            2. 12.10.1.2.7.2 DCC FIFO in continuous capture mode
            3. 12.10.1.2.7.3 DCC FIFO Details
            4. 12.10.1.2.7.4 DCC FIFO Debug mode behavior
          8. 12.10.1.2.8 DCC Count read registers
      2. 12.10.2 Error Signaling Module (ESM)
        1. 12.10.2.1 ESM Overview
          1. 12.10.2.1.1 ESM Features
          2. 12.10.2.1.2 ESM Ports
        2. 12.10.2.2 ESM Environment
        3. 12.10.2.3 ESM Functional Description
          1. 12.10.2.3.1 ESM Interrupt Requests
            1. 12.10.2.3.1.1 ESM Configuration Error Interrupt
            2. 12.10.2.3.1.2 ESM Low Priority Error Interrupt
              1. 12.10.2.3.1.2.1 ESM Low Priority Error Level Event
              2. 12.10.2.3.1.2.2 ESM Low Priority Error Pulse Event
            3. 12.10.2.3.1.3 ESM High Priority Error Interrupt
              1. 12.10.2.3.1.3.1 ESM High Priority Error Level Event
              2. 12.10.2.3.1.3.2 ESM High Priority Error Pulse Event
          2. 12.10.2.3.2 ESM Error Event Inputs
          3. 12.10.2.3.3 ESM Error Pin Output
          4. 12.10.2.3.4 PWM Mode
          5. 12.10.2.3.5 ESM Minimum Time Interval
          6. 12.10.2.3.6 ESM Protection for Registers
          7. 12.10.2.3.7 ESM Clock Stop
      3. 12.10.3 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 12.10.3.1 MCRC Overview
          1. 12.10.3.1.1 MCRC Features
          2. 12.10.3.1.2 MCRC Ports
        2. 12.10.3.2 MCRC Functional Description
          1. 12.10.3.2.1  MCRC Block Diagram
          2. 12.10.3.2.2  MCRC General Operation
          3. 12.10.3.2.3  MCRC Modes of Operation
            1. 12.10.3.2.3.1 AUTO Mode
            2. 12.10.3.2.3.2 Semi-CPU Mode
            3. 12.10.3.2.3.3 Full-CPU Mode
          4. 12.10.3.2.4  PSA Signature Register
          5. 12.10.3.2.5  PSA Sector Signature Register
          6. 12.10.3.2.6  CRC Value Register
          7. 12.10.3.2.7  Raw Data Register
          8. 12.10.3.2.8  Example DMA Controller Setup
            1. 12.10.3.2.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 12.10.3.2.8.2 AUTO Mode Using Software Trigger
            3. 12.10.3.2.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 12.10.3.2.9  Pattern Count Register
          10. 12.10.3.2.10 Sector Count Register/Current Sector Register
          11. 12.10.3.2.11 Interrupts
            1. 12.10.3.2.11.1 Compression Complete Interrupt
            2. 12.10.3.2.11.2 CRC Fail Interrupt
            3. 12.10.3.2.11.3 Overrun Interrupt
            4. 12.10.3.2.11.4 Underrun Interrupt
            5. 12.10.3.2.11.5 Timeout Interrupt
            6. 12.10.3.2.11.6 Interrupt Offset Register
            7. 12.10.3.2.11.7 Error Handling
          12. 12.10.3.2.12 Power Down Mode
          13. 12.10.3.2.13 Emulation
        3. 12.10.3.3 MCRC Programming Examples
          1. 12.10.3.3.1 Example: Auto Mode Using Time Based Event Triggering
            1. 12.10.3.3.1.1 DMA Setup
            2. 12.10.3.3.1.2 Timer Setup
            3. 12.10.3.3.1.3 CRC Setup
          2. 12.10.3.3.2 Example: Auto Mode Without Using Time Based Triggering
            1. 12.10.3.3.2.1 DMA Setup
            2. 12.10.3.3.2.2 CRC Setup
          3. 12.10.3.3.3 Example: Semi-CPU Mode
            1. 12.10.3.3.3.1 DMA Setup
            2. 12.10.3.3.3.2 Timer Setup
            3. 12.10.3.3.3.3 CRC Setup
          4. 12.10.3.3.4 Example: Full-CPU Mode
            1. 12.10.3.3.4.1 CRC Setup
      4. 12.10.4 ECC Aggregator
        1. 12.10.4.1 ECC Aggregator Overview
          1. 12.10.4.1.1 ECC Aggregator Features
          2. 12.10.4.1.2 ECC Aggregator Ports
        2. 12.10.4.2 ECC Aggregator Functional Description
          1. 12.10.4.2.1 ECC Aggregator Block Diagram
          2. 12.10.4.2.2 ECC Aggregator Register Groups
          3. 12.10.4.2.3 Read Access to the ECC Control and Status Registers
          4. 12.10.4.2.4 Serial Write Operation
          5. 12.10.4.2.5 Interrupts
          6. 12.10.4.2.6 Inject Only Mode
        3. 12.10.4.3 ECC Aggregator Configurations
          1.        3242
          2.        3243
          3.        3244
          4.        3245
          5.        3246
          6.        3247
          7.        3248
          8.        3249
          9.        3250
          10.        3251
          11.        3252
          12.        3253
          13.        3254
          14.        3255
          15.        3256
          16.        3257
          17.        3258
          18.        3259
          19.        3260
          20.        3261
          21.        3262
          22.        3263
          23.        3264
          24.        3265
          25.        3266
          26.        3267
          27.        3268
          28.        3269
          29.        3270
          30.        3271
          31.        3272
          32.        3273
          33.        3274
          34.        3275
          35.        3276
          36.        3277
          37.        3278
          38.        3279
          39.        3280
          40.        3281
          41.        3282
          42.        3283
          43.        3284
          44.        3285
          45.        3286
          46.        3287
          47.        3288
          48.        3289
          49.        3290
          50.        3291
          51.        3292
          52.        3293
          53.        3294
          54.        3295
          55.        3296
  15. 13On-Chip Debug
  16. 14Revision History
Table 12-456 Properties of ECC Aggregator Instance ECC_AGGR5
RAM ID NameRAM IDECC TypeInject TypeAccessible FlagRow WidthRAM Size
RC_TO_HC2_VBUSM_L0_STOG_3_WR_RAMECC2ECC WrapperInject with error captureYes881 KB
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_WR_RAMECC4ECC WrapperInject with error captureYes88352 B
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_RD_RAMECC7ECC WrapperInject with error captureYes8844 B
RC_TO_HC2_VBUSM_L0_STOG_3_RD_RAMECC19ECC WrapperInject with error captureYes881 KB
RC_TO_HC2_VBUSM_L1_STOG_4_RD_RAMECC22ECC WrapperInject with error captureYes881 KB
RC_TO_HC2_VBUSM_L1_STOG_4_WR_RAMECC24ECC WrapperInject with error captureYes881 KB
Table 12-457 Properties of ECC Aggregator Instance ECC_AGGR5
RAM ID NameRAM IDECC TypeInject TypeAccessible FlagMax Number of Checkers
HC_PIPE3_PHYS_IRC_TO_HC_CFG_P2P_BUSECC0EDC InterconnectInject with error captureYes11
HC2_TO_RC_VBUSM_L1_MTOG_EDC_CTRL1EDC InterconnectInject with error captureYes1
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC3EDC InterconnectInject with error captureYes13
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_05EDC InterconnectInject with error captureYes256
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL6EDC InterconnectInject with error captureYes131
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC8EDC InterconnectInject with error captureYes200
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_19EDC InterconnectInject with error captureYes95
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC10EDC InterconnectInject with error captureYes19
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC11EDC InterconnectInject with error captureYes31
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC12EDC InterconnectInject with error captureYes17
HC2_TO_RC_VBUSM_L0_MTOG_EDC_CTRL13EDC InterconnectInject with error captureYes1
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC14EDC InterconnectInject with error captureYes16
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC15EDC InterconnectInject with error captureYes13
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC16EDC InterconnectInject with error captureYes17
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_117EDC InterconnectInject with error captureYes31
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC18EDC InterconnectInject with error captureYes7
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC20EDC InterconnectInject with error captureYes7
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC21EDC InterconnectInject with error captureYes13
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_023EDC InterconnectInject with error captureYes256
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_125EDC InterconnectInject with error captureYes256
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_026EDC InterconnectInject with error captureYes256
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_027EDC InterconnectInject with error captureYes256
HC2_CBASS_DEFAULT_ERR_ HC2_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC28EDC InterconnectInject with error captureYes5
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC29EDC InterconnectInject with error captureYes4
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC30EDC InterconnectInject with error captureYes19
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC31EDC InterconnectInject with error captureYes38
HC2_CBASS_INT_DMSC_SCR_ HC2_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC32EDC InterconnectInject with error captureYes42
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC33EDC InterconnectInject with error captureYes15
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC34EDC InterconnectInject with error captureYes25
HC2_CBASS_DEFAULT_MMRS_ HC2_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC35EDC InterconnectInject with error captureYes9
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC36EDC InterconnectInject with error captureYes42
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_137EDC InterconnectInject with error captureYes256
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC38EDC InterconnectInject with error captureYes72
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC39EDC InterconnectInject with error captureYes72
HC_PIPE3_PHYS_IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC40EDC InterconnectInject with error captureYes41
HC_PIPE3_PHYS_IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC41EDC InterconnectInject with error captureYes45
HC_PIPE3_PHYS_IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC42EDC InterconnectInject with error captureYes41
HC_PIPE3_PHYS_IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC43EDC InterconnectInject with error captureYes45
HC_PIPE3_PHYS_IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC44EDC InterconnectInject with error captureYes41
HC_PIPE3_PHYS_IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC45EDC InterconnectInject with error captureYes45
HC_PIPE3_PHYS_IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC46EDC InterconnectInject with error captureYes41
HC_PIPE3_PHYS_IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC47EDC InterconnectInject with error captureYes45
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC48EDC InterconnectInject with error captureYes72
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC49EDC InterconnectInject with error captureYes72
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_ RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC50EDC InterconnectInject with error captureYes11
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_251EDC InterconnectInject with error captureYes175
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_052EDC InterconnectInject with error captureYes256
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_153EDC InterconnectInject with error captureYes95
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC54EDC InterconnectInject with error captureYes13
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC55EDC InterconnectInject with error captureYes13
MAIN_HC_ECC_AGGR_EDC_CTRL56EDC InterconnectInject with error captureYes6
Table 12-458 EDC checkers information for ECC Aggregator Instance ECC_AGGR5
Protected InterconnectGroup IDWidthChecker Type
HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC01Parity
HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC132Parity
HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC21Redundant
HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC31Redundant
HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC41Redundant
HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC51Redundant
HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC61Redundant
HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC718Parity
HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC820Parity
HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC918Parity
HC_PIPE3_PHYS__IRC_TO_HC_CFG_P2P_BUSECC1020Parity
HC2_TO_RC_VBUSM_L1_MTOG_EDC_CTRL048Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC01Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC132Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC21Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC31Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC41Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC51Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC61Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC78Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC88Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC98Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC108Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC111Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_SRC_BUSECC121Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_002Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_012Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0210Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_032Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_043Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_051Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_061Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_078Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_081Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_092Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0101Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01112Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0122Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0132Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0144Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0152Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0162Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01710Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0182Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0193Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0201Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0211Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0228Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0231Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0242Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0251Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02612Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0272Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0282Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0294Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0302Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0312Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_03210Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0332Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0343Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0351Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0361Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0378Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0381Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0392Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0401Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_04112Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0422Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0432Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0444Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0452Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0462Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_04710Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0482Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0493Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0501Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0511Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0528Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0531Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0542Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0551Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_05612Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0572Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0582Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0594Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0602Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0612Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_06210Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0632Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0643Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0651Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0661Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0678Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0681Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0692Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0701Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_07112Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0722Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0732Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0744Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0752Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0762Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_07710Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0782Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0793Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0801Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0811Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0828Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0831Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0842Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0851Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_08612Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0872Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0882Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0894Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0902Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0912Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_09210Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0932Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0943Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0951Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0961Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0978Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0981Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0992Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01001Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_010112Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01022Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01032Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01044Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01052Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01062Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_010710Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01082Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01093Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01101Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01111Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01128Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01131Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01142Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01151Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_011612Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01172Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01182Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01194Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01202Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01212Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_012210Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01232Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01243Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01251Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01261Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01278Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01281Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01292Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01301Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_013112Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01322Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01332Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01344Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01352Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01362Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_013710Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01382Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01393Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01401Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01411Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01428Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01431Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01442Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01451Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_014612Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01472Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01482Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01494Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01502Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01512Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_015210Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01532Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01543Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01551Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01561Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01578Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01581Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01592Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01601Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_016112Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01622Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01632Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01644Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01652Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01662Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_016710Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01682Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01693Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01701Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01711Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01728Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01731Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01742Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01751Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_017612Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01772Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01782Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01794Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01801Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_018132EDC
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01821Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_018316Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01844Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01853Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01865Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_018712Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01884Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_018912Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01901Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01911Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01921Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01931Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01942Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01952Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01961Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_019732EDC
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_01981Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_019910Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02004Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02013Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_020212Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02034Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_020412Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02051Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02061Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02071Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02081Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02092Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02101Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_021132EDC
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02121Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_021321Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02144Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02153Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02164Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_021712Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02184Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_021912Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02201Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02211Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02221Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02231Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02242Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02252Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02262Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02272Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02281Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_022932EDC
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02301Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_023116Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02324Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02333Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02345Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_023512Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02364Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_023712Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02381Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02391Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02401Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02411Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02422Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02431Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_024432EDC
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02451Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_024610Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02474Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02483Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_024912Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02504Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_025112Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02521Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02531Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02541Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_02551Redundant
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL01Redundant
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL11Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL24Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL310Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL432EDC
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL51Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL62Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL72Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL81Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL930Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL102Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL115Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1210Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1312Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL144Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL153Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL161Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL171Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL181Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL191Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL202Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL2110Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL2210Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL2312Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL244Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL253Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL261Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL2710Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL283Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL293Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL301Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL311Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL321Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL331Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL343Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL351Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL361Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL371Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL3830Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL396Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL406Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL416Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL422Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL4310Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL446Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL455Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL4632Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL471Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL484Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL4912Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL5010Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL5148Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL521Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL531Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL541Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL551Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL561Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL5711Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL5832Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL595Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL605Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL615Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL625Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL635Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL645Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL655Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL665Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL675Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL685Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL695Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL705Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL715Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL725Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL735Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL745Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL755Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL765Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL775Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL785Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL795Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL805Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL815Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL825Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL835Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL845Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL855Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL865Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL875Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL885Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL895Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL905Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL9119Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL9219Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL931Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL941Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL951Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL961Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL9710Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL983Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL992Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1004Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1015Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1024Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1032Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1042Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1052Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1062Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL10755Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL10855Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL10912Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1104Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL11112Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL11210Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1133Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1141Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1158Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1164Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL11712Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL11812Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL11910Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL12010Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1211Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1221Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1231Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1241Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1253Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1263Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1273Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1283Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1291Parity
HC2_TO_HC_CFG_VBUSM_L0_STOG_5_EDC_CTRL1308Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC01Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC148Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC21Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC34Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC43Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC51Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC64Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC74Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC82Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC91Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC101Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC111Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC121Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1310Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC141Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1512Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC164Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC171Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC181Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1910Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC201Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC2112Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC224Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC231Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC241Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC2510Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC261Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC2712Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC284Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC291Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC301Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC3110Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC321Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC3312Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC344Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC351Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC361Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC3710Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC381Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC3912Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC404Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC411Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC421Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC4310Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC441Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC4512Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC464Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC471Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC481Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC4910Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC501Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC5112Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC524Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC531Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC541Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC5510Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC561Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC5712Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC584Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC591Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC601Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC6110Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC621Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC6312Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC644Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC651Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC661Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC6710Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC681Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC6912Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC704Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC711Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC721Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC7310Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC741Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC7512Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC764Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC771Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC781Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC7910Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC801Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC8112Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC824Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC831Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC841Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC8510Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC861Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC8712Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC884Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC891Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC901Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC9110Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC921Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC9312Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC944Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC951Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC964Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC9713Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC9818Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC9914Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC10015Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1013Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1021Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1033Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC10426Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1053Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1063Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1071Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1083Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC10926Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1103Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1113Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1121Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1133Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC11426Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1153Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1163Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1171Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1183Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC11926Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1203Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1213Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1221Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1233Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC12426Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1253Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1263Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1271Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1283Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC12926Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1303Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1313Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1321Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1333Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC13426Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1353Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1363Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1371Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1383Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC13926Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1403Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1413Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1421Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1433Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC14426Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1453Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1463Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1471Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1483Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC14926Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1503Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1513Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1521Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1533Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC15426Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1553Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1563Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1571Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1583Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC15926Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1603Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1613Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1621Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1633Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC16426Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1653Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1661Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1671Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC16812Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1691Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1704Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1713Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1725Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC17310Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1741Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1751Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1761Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC17748Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1784Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1793Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1805Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC18110Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1821Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1831Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1841Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1858Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1863Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1871Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1883Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC18926Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1903Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1911Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1921Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1931Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC19432EDC
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1951Redundant
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1961Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC19710Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC19810Parity
HC2_CBASS_SCRP_32B_CLK4_SCR_ HC2_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC1991Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_107Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_117Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_127Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_137Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_147Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_157Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_167Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_177Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_187Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_197Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1107Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1117Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1127Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1137Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1147Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1157Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1167Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1177Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1187Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1197Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1207Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1217Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1227Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1237Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1247Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1257Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1267Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1277Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1287Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1297Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1307Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1317Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1327Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1337Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1347Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1357Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1367Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1377Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1387Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1397Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1407Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1417Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1427Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1437Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1447Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1457Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1467Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1477Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1487Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1497Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1507Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1517Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1527Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1537Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1547Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1557Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1567Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1577Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1587Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1597Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1607Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1617Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1627Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1637Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1647Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1657Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1667Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1677Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1687Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1697Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1707Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_17150Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_17250Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_17312Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1744Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_17512Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_17610Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1773Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1781Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1798Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1804Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_18112Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_18212Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_18310Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_18410Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1851Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1861Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1871Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1881Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1895Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1903Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1913Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1923Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1931Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_1948Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC01Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC11Redundant
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC21Redundant
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC31Redundant
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC410Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC53Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC63Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC71Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC81Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC92Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC103Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC111Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC1210Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC135Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC143Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC154Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC162Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC1710Parity
HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC183Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC032Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC132Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC21Redundant
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC31Redundant
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC41Redundant
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC51Redundant
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC61Redundant
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC71Redundant
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC848Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC93Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC103Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC112Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC123Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC131Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC1410Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC152Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC162Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC172Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC181Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC191Redundant
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC202Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC213Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC2210Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC231Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC241Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC251Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC261Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC272Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC283Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC293Parity
HC_CFG_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_M2P_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC302Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC01Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC132Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC21Redundant
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC31Redundant
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC410Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC53Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC63Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC71Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC81Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC92Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC103Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC111Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC1210Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC135Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC143Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC154Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC162Parity
HC2_TO_RC_VBUSM_L0_MTOG_EDC_CTRL048Parity
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC032Parity
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC11Parity
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC21Redundant
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC31Redundant
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC41Redundant
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC51Redundant
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC61Redundant
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC71Redundant
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC814Parity
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC914Parity
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC1014Parity
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC1114Parity
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC1232EDC
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC138Parity
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC148Parity
HC2_CBASS_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_P2M_BRIDGE_EXPORT_ HC2_TO_HC_CFG_VBUSM_L0_BRIDGE_BUSECC1514Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC01Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC132Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC21Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC31Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC41Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC51Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC61Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC78Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC88Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC98Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC108Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC111Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_SRC_BUSECC121Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC01Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC132Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC21Redundant
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC31Redundant
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC410Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC53Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC63Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC71Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC81Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC92Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC103Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC111Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC1210Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC135Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC143Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC154Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC162Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_102Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_112Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_121Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1332EDC
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_141Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1516Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_164Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_173Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_185Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1912Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1104Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_11112Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1121Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1131Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1141Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1151Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1162Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1171Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_11832EDC
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1191Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_12012Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1214Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1223Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_12312Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1244Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_12512Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1261Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1271Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1281Parity
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1291Redundant
HC2_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1302Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC01Redundant
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC11Redundant
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC21Redundant
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC310Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC43Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC51Parity
HC2_CBASS_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_ HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC61Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC01Redundant
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC11Redundant
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC21Redundant
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC310Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC43Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC51Parity
HC2_CBASS_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_ MAIN_HC_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC61Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC01Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC132Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC21Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC31Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC41Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC51Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC61Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC78Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC88Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC98Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC108Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC111Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_HC2CFG_0_CFG_BRIDGE_BUSECC121Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_001Redundant
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_011Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_024Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0310Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0432EDC
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_051Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_062Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_072Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_081Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0930Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0102Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0117Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01210Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01312Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0144Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0153Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0161Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0171Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0181Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0191Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0207Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02110Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02210Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02312Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0244Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0253Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0261Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02710Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0283Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0293Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0301Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0311Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0321Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0331Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0345Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0351Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0361Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0371Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_03830Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0396Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0406Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0416Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0422Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_04310Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0448Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0457Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_046128Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0471Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0484Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_04912Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_05010Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_05148Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0521Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0531Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0541Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0551Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0561Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_05715Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_058128Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0597Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0607Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0617Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0627Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0637Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0647Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0657Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0667Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0677Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0687Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0697Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0707Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0717Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0727Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0737Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0747Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0757Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0767Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0777Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0787Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0797Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0807Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0817Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0827Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0837Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0847Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0857Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0867Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0877Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0887Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0897Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0907Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0917Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0927Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0937Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0947Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0957Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0967Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0977Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0987Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0997Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01007Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01017Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01027Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01037Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01047Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01057Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01067Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01077Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01087Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01097Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01107Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01117Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01127Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01137Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01147Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01157Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01167Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01177Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01187Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01197Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01207Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01217Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01227Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01237Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01247Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01257Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01267Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01277Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01287Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01297Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01307Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01317Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01327Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01337Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01347Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01357Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01367Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01377Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01387Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01397Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01407Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01417Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01427Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01437Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01447Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01457Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01467Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01477Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01487Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01497Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01507Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01517Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01527Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01537Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01547Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01557Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01567Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01577Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01587Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01597Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01607Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01617Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01627Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01637Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01647Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01657Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01667Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01677Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01687Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01697Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01707Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01717Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01727Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01737Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01747Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01757Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01767Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01777Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01787Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01797Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01807Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01817Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01827Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01837Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01847Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01857Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01867Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_018717Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_018817Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01891Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01901Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01911Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01921Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_019310Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01948Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01957Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0196128Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_019715Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_0198128Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_01997Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02007Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02017Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02027Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02037Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02047Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02057Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02067Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02077Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02087Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02097Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02107Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02117Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02127Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02137Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02147Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02157Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02167Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02177Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02187Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02197Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02207Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02217Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02227Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02237Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02247Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02257Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02267Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02277Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02287Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02297Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02307Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02317Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02327Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02337Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02347Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02357Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02367Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02377Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02387Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02397Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02407Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02417Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02427Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02437Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02447Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02457Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02467Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02477Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02487Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02497Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02507Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02517Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02527Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02537Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02547Parity
RC_TO_HC2_VBUSM_L1_STOG_4_EDC_CTRL_BUSECC_02557Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_101Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_111Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1212Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1310Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1410Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_151Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_161Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_171Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_181Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_195Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11032EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11132EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11232EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11332EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1143Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1151Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11612Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11710Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1183Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11948Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12010Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1212Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1224Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1231Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1242Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1258Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12643Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1271Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1281Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12912Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_13010Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_13110Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1321Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1331Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1341Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1351Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1365Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_13732EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_13832EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_13932EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_14032EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1413Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_14212Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_14348Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_14410Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1452Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1464Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1471Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1482Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_14943Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1501Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1511Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1521Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_15312Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_15410Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1553Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_15612Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_15748Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_15810Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1592Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1604Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1611Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1622Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_16343Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1641Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1651Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_16612Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_16710Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_16810Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1691Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1701Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1711Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1721Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1735Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_17432EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_17532EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_17632EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_17732EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1783Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_17912Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_18048Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_18110Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1822Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1834Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1841Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1852Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_18643Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1871Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1881Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1891Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_19012Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_19110Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1923Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_19312Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_19448Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_19510Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1962Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1974Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1981Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1992Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_110043Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11011Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11021Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_110312Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_110410Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_110510Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11061Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11071Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11081Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11091Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11105Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_111132EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_111232EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_111332EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_111432EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11153Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_111612Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_111748Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_111810Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11192Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11204Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11211Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11222Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_112329Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11241Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11251Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11261Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_112712Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_112810Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11293Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_113012Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_113148Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_113210Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11332Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11344Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11351Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11362Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_113729Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11381Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11391Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_114012Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_114110Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_114210Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11431Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11441Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11451Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11461Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11475Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_114832EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_114932EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_115032EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_115132EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11523Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_115312Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_115448Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_115510Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11562Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11574Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11581Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11592Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_116029Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11611Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11621Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11631Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_116412Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_116510Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11663Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_116712Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_116848Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_116910Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11702Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11714Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11721Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11732Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_117429Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11751Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_117612Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11771Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_117810Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_117948Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11802Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11813Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_118212Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11834Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11844Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11853Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11863Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11871Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11881Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11892Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11902Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11918Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11921Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11931Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11941Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11953Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11962Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11972Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11982Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_11992Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12001Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_120112Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12022Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12034Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12042Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12051Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_120612Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12071Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_120810Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12091Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12101Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12115Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_121216Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12131Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_121432EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_121532EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_121632EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_121732EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12181Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12191Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12202Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12211Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_122212Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12231Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_122410Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_122548Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12262Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12273Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_122812Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12294Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12304Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12313Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12323Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12331Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12341Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12352Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12362Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12378Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12381Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12391Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12401Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12413Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12422Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12432Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12442Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12452Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12461Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_124712Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12482Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12494Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12502Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12511Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_125212Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12531Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_125410Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_12551Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_001Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0148Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_021Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_034Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_043Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_054Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_064Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_072Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_081Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_091Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0101Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0111Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0121Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01348Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0141Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0154Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0163Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0174Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0184Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0192Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0201Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0211Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0221Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0231Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0241Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02548Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0261Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0274Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0283Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0294Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0304Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0312Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0321Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0331Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0341Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0351Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0361Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_03748Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0381Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0394Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0403Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0414Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0424Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0432Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0441Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0451Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0461Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0471Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0481Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_04948Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0501Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0514Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0523Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0534Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0544Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0552Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0561Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0571Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0581Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0591Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0601Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_06148Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0621Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0634Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0643Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0654Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0664Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0672Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0681Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0691Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0701Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0711Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0721Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_07348Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0741Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0754Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0763Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0774Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0784Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0792Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0801Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0811Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0821Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0831Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0841Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_08548Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0861Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0874Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0883Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0894Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0904Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0912Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0921Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0931Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0941Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0951Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0961Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_09748Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0981Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_0994Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01003Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01014Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01024Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01032Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01041Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01051Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01061Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01071Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01081Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_010948Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01101Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01114Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01123Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01134Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01144Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01152Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01161Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01171Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01181Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01191Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01201Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_012148Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01221Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01234Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01243Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01254Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01264Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01272Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01281Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01291Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01301Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01311Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01321Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_013348Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01341Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01354Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01363Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01374Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01384Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01392Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01401Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01411Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01421Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01431Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01441Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_014548Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01461Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01474Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01483Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01494Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01504Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01512Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01521Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01531Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01541Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01551Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01561Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_015748Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01581Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01594Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01603Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01614Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01624Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01632Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01641Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01651Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01661Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01671Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01681Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_016948Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01701Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01714Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01723Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01734Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01744Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01752Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01761Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01771Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01781Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01791Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01801Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_018148Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01821Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01834Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01843Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01854Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01864Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01872Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01881Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01891Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01901Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01911Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01921Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_019348Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01941Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01954Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01963Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01974Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01984Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_01992Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02001Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02011Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02021Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02031Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02041Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_020548Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02061Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02074Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02083Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02094Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02104Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02112Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02121Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02131Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02141Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02151Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02161Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_021748Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02181Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02194Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02203Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02214Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02224Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02232Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02241Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02251Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02261Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02271Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02281Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_022910Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_023010Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02311Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02321Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02331Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_023412Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02354Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02363Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02371Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_023812Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02394Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02401Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_024110Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_024210Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02431Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02441Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02451Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_024612Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02474Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02483Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02491Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_025012Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02514Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02521Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_025310Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_025410Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_02551Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_002Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_012Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0210Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_032Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_043Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_051Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_061Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_078Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_081Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_092Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0101Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01112Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0122Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0132Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0144Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0151Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0162Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0172Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01810Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0192Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0203Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0211Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0221Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0238Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0241Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0252Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0261Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02712Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0282Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0292Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0304Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0311Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0322Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0332Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_03410Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0352Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0363Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0371Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0381Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0398Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0401Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0412Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0421Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_04312Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0442Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0452Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0464Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0471Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0482Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0492Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_05010Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0512Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0523Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0531Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0541Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0558Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0561Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0572Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0581Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_05912Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0602Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0612Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0624Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0631Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0642Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0652Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_06610Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0672Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0683Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0691Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0701Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0718Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0721Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0732Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0741Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_07512Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0762Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0772Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0784Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0791Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0802Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0812Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_08210Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0832Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0843Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0851Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0861Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0878Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0881Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0892Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0901Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_09112Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0922Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0932Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0944Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0951Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0961Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0971Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0981Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_09912Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_010010Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01013Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_010248Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_010310Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01042Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01054Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01061Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01072Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_010843Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01091Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01101Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_011112Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_011210Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_011310Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01141Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01151Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01161Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01171Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01185Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_011932EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_012032EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_012132EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_012232EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01233Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_012448Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_012510Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01262Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01274Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01281Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01292Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_013043Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01311Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01321Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_013312Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_013410Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_013510Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01361Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01371Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01381Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01391Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01405Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_014132EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_014232EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_014332EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_014432EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01453Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_014612Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_014748Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_014810Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01492Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01504Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01511Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01522Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_015329Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01541Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01551Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01561Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_015712Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_015810Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01593Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_016012Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_016148Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_016210Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01632Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01644Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01651Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01662Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_016729Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01681Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01691Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01701Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_017112Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_017210Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_017310Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01741Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01751Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01761Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01771Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01785Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01793Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01803Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01811Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_018232EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_018332EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_018432EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_018532EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01863Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01871Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_018812Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_018910Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01903Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01911Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_019226Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01931Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01941Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01951Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_019612Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_019710Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_019810Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_01991Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02001Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02011Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02021Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02035Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02043Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02053Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02061Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_020732EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_020832EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_020932EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_021032EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02113Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02121Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_021312Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_021410Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02153Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02161Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_021726Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02181Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02191Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_022012Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_022110Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_022210Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02231Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02241Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02251Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02261Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02275Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_022832EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_022932EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_023032EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_023132EDC
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02323Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_023312Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_023448Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_023510Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02362Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02374Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02381Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02392Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_024029Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02411Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02421Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02431Redundant
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_024412Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_024510Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02463Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_024712Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_024848Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_024910Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02502Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02514Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02521Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02532Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_025429Parity
HC2_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_02551Redundant
HC2_CBASS_CBASS_DEFAULT_ERR_ HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC01Redundant
HC2_CBASS_CBASS_DEFAULT_ERR_ HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC11Parity
HC2_CBASS_CBASS_DEFAULT_ERR_ HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC24Parity
HC2_CBASS_CBASS_DEFAULT_ERR_ HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC310Parity
HC2_CBASS_CBASS_DEFAULT_ERR_ HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC432EDC
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC01Redundant
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC11Redundant
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC215Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC33Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC01Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC11Redundant
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC21Redundant
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC31Redundant
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC415Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC53Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC63Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC71Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC81Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC92Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC103Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC111Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC1210Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC135Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC143Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC154Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC162Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC1715Parity
HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC183Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC01Redundant
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC132EDC
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC21Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC348Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC44Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC53Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC61Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC71Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC810Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC95Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC1012Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC114Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC1212Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC133Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC143Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC152Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC163Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC171Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC181Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC192Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC202Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC218Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC221Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC231Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC241Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC253Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC262Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC272Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC282Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC292Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC301Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC312Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC324Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC3312Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC342Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC351Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC3612Parity
HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC371Redundant
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC01Redundant
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC118Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC21Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC34Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC43Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC51Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC64Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC74Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC82Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC91Redundant
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC101Redundant
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC111Redundant
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC121Redundant
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC131Redundant
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC1412Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC154Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC161Redundant
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC171Redundant
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC1810Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC191Redundant
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC2012Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC214Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC221Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC234Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC247Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC252Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC263Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC273Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC2826Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC293Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC303Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC3126Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC323Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC331Redundant
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC341Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC351Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC3632EDC
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC371Redundant
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC381Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC3910Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC4010Parity
HC2_CBASS_CBASS_INT_DMSC_SCR_ HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC411Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC01Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC11Redundant
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC215Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC33Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC43Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC51Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC61Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC72Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC83Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC91Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC1010Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC115Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC123Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC134Parity
MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC142Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC01Redundant
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC132EDC
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC21Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC324Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC44Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC53Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC61Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC71Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC810Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC912Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC104Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC1112Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC122Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC133Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC142Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC152Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC168Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC171Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC181Parity
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC191Redundant
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC2032EDC
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC211Redundant
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC221Redundant
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC2332EDC
MAIN_HC2_FW_CBASS_0_ MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC241Redundant
HC2_CBASS_CBASS_DEFAULT_MMRS_ HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC032Parity
HC2_CBASS_CBASS_DEFAULT_MMRS_ HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC132Parity
HC2_CBASS_CBASS_DEFAULT_MMRS_ HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC232Parity
HC2_CBASS_CBASS_DEFAULT_MMRS_ HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC31Redundant
HC2_CBASS_CBASS_DEFAULT_MMRS_ HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC41Parity
HC2_CBASS_CBASS_DEFAULT_MMRS_ HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC54Parity
HC2_CBASS_CBASS_DEFAULT_MMRS_ HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC615Parity
HC2_CBASS_CBASS_DEFAULT_MMRS_ HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC74Parity
HC2_CBASS_CBASS_DEFAULT_MMRS_ HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC832EDC
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC01Redundant
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC110Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC21Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC34Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC43Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC51Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC64Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC74Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC82Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC91Redundant
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC101Redundant
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC111Redundant
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC121Redundant
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC131Redundant
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC1412Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC154Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC161Redundant
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC171Redundant
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC1810Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC191Redundant
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC2012Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC214Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC221Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC234Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC247Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC252Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC263Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC273Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC2826Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC293Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC303Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC3126Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC323Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC331Redundant
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC341Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC351Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC3632EDC
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC371Redundant
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC381Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC3910Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC4010Parity
HC2_CBASS_ERR_SCR_ HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC411Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_101Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_111Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1212Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_134Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_143Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_151Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1612Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_174Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_181Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1910Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11010Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1111Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1121Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1131Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11412Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1154Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1163Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1171Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11812Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1194Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1201Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12110Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12210Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1231Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1241Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1251Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12612Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1274Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1283Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1291Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_13012Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1314Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1321Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_13310Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_13410Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1351Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1361Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1371Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_13812Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1394Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1403Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1411Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_14212Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1434Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1441Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_14510Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_14610Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1471Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1481Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1491Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_15012Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1514Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1523Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1531Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_15412Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1554Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1561Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_15710Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_15810Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1591Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1601Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1611Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_16212Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1634Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1643Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1651Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_16612Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1674Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1681Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_16910Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_17010Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1711Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1721Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1731Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_17412Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1754Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1763Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1771Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_17812Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1794Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1801Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1814Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1828Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_18317Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_18411Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_18563Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_18635Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_18710Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1888Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_18917Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_19011Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_19163Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_19235Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_19310Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1947Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_19516Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_19610Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_19764Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_19825Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_1999Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11007Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_110116Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_110210Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_110364Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_110425Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11059Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11061Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11071Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11081Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11091Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11101Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11111Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11121Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11133Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11143Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11158Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11168Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11178Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11188Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11193Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11207Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_112116Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_112210Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_112364Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_112425Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11259Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11261Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11271Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11281Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11291Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11301Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11311Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11321Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11333Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11343Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11358Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11368Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11378Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11388Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11393Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11407Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_114116Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_114210Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_114364Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_114425Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11459Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11467Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_114716Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_114810Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_114964Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_115025Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11519Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11527Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_115316Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_115410Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_115564Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_115625Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11579Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11588Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_115917Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_116011Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_116163Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_116235Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_116310Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11641Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11651Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11661Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11671Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11681Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11691Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11701Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11713Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11723Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11738Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11748Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11758Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11768Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11773Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11788Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_117917Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_118011Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_118163Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_118235Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_118310Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11841Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11851Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11861Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11871Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11881Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11891Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11901Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11913Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11923Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11938Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11948Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11958Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11968Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11973Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_11988Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_119917Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_120011Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_120163Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_120235Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_120310Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12048Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_120517Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_120611Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_120763Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_120835Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_120910Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12108Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_121117Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_121211Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_121363Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_121435Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_121510Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12167Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_121716Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_121810Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_121964Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_122025Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12219Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12227Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_122316Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_122410Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_122564Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_122625Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12279Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12287Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_122916Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_123010Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_123164Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_123225Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12339Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12347Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_123516Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_123610Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_123764Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_123825Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12399Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12406Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_124111Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12429Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_124364Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_124416Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12458Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12466Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_124711Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12489Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_124964Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_125016Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12518Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12523Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_12531Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_125460Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_125559Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC024Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC11Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC21Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC31Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC448Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC510Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC61Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC73Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC83Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC91Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC101Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC119Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1210Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1310Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC141Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC151Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1648Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC171Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC181Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1910Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC201Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC211Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC221Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC2310Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC241Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC251Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC261Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC271Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC2810Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC299Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC301Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC3110Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC3210Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC331Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC345Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC359Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC361Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC371Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC383Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC393Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4010Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC411Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC421Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4310Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4410Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC451Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC461Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC473Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4810Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC493Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC508Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC511Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC521Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC538Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC548Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC552Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC562Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC573Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC581Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC598Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC608Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC618Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC628Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC631Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC641Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC658Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC668Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC672Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC682Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC693Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC701Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC718Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC024Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC11Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC21Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC31Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC448Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC510Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC61Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC73Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC83Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC91Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC101Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC119Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1210Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1310Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC141Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC151Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1648Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC171Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC181Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1910Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC201Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC211Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC221Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC2310Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC241Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC251Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC261Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC271Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC2810Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC299Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC301Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC3110Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC3210Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC331Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC345Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC359Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC361Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC371Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC383Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC393Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4010Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC411Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC421Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4310Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4410Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC451Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC461Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC473Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4810Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC493Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC508Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC511Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC521Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC538Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC548Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC552Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC562Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC573Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC581Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC598Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC608Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC618Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC628Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC631Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC641Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC658Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC668Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC672Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC682Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC693Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC701Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC718Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC024Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC11Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC21Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC31Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC448Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC510Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC61Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC73Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC83Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC91Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1010Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC111Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC121Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC131Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1410Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC151Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC161Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1710Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1810Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC191Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC201Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC213Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC2210Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC233Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC241Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC251Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC2618Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC273Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC288Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC298Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC308Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC318Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC328Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC338Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC348Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC357Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC363Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC371Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC3820Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC393Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC407Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC01Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC11Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC29Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC310Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC410Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC51Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC61Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC748Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC81Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC91Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1010Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC111Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC121Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC131Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC141Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1510Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC169Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC171Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1810Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1910Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC201Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC215Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC229Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC231Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC243Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC253Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC261Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC271Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC283Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC297Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC308Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC3118Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC3218Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC333Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC348Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC358Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC368Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC378Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC388Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC398Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC408Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC417Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC423Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC431Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC4420Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC024Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC11Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC21Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC31Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC448Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC510Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC61Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC73Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC83Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC91Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1010Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC111Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC121Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC131Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1410Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC151Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC161Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1710Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1810Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC191Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC201Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC213Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC2210Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC233Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC241Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC251Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC2618Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC273Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC288Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC298Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC308Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC318Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC328Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC338Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC348Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC357Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC363Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC371Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC3820Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC393Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC407Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC01Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC11Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC29Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC310Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC410Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC51Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC61Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC748Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC81Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC91Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1010Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC111Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC121Redundant
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC131Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC141Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1510Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC169Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC171Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1810Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1910Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC201Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC215Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC229Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC231Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC243Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC253Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC261Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC271Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC283Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC297Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC308Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC3118Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC3218Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC333Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC348Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC358Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC368Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC378Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC388Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC398Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC408Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC417Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC423Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC431Parity
HC_PIPE3_PHYS__IHC2_TO_RC_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC4420Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC024Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC11Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC21Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC31Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC448Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC510Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC61Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC73Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC83Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC91Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1010Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC111Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC121Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC131Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1410Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC151Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC161Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1710Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1810Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC191Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC201Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC213Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC2210Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC233Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC241Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC251Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC2618Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC273Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC288Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC298Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC308Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC318Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC328Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC338Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC348Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC357Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC363Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC371Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC3820Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC393Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC407Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC01Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC11Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC29Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC310Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC410Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC51Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC61Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC748Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC81Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC91Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1010Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC111Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC121Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC131Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC141Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1510Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC169Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC171Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1810Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1910Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC201Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC215Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC229Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC231Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC243Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC253Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC261Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC271Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC283Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC297Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC308Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC3118Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC3218Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC333Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC348Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC358Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC368Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC378Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC388Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC398Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC408Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC417Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC423Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC431Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L0_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC4420Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC024Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC11Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC21Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC31Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC448Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC510Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC61Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC73Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC83Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC91Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1010Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC111Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC121Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC131Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1410Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC151Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC161Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1710Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC1810Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC191Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC201Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC213Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC2210Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC233Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC241Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC251Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC2618Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC273Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC288Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC298Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC308Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC318Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC328Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC338Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC348Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC357Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC363Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC371Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC3820Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC393Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_SRC_EDC_CTRL_BUSECC407Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC01Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC11Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC29Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC310Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC410Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC51Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC61Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC748Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC81Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC91Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1010Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC111Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC121Redundant
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC131Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC141Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1510Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC169Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC171Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1810Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC1910Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC201Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC215Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC229Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC231Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC243Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC253Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC261Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC271Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC283Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC297Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC308Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC3118Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC3218Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC333Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC348Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC358Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC368Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC378Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC388Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC398Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC408Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC417Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC423Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC431Parity
HC_PIPE3_PHYS__IRC_TO_HC2_VBUSM_L1_ 128B_M2M_RETIME_DST_EDC_CTRL_BUSECC4420Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC024Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC11Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC21Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC31Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC448Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC510Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC61Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC73Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC83Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC91Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC101Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC119Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1210Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1310Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC141Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC151Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1648Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC171Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC181Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1910Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC201Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC211Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC221Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC2310Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC241Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC251Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC261Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC271Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC2810Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC299Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC301Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC3110Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC3210Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC331Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC345Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC359Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC361Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC371Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC383Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC393Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4010Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC411Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC421Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4310Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4410Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC451Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC461Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC473Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4810Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC493Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC508Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC511Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC521Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC538Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC548Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC552Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC562Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC573Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC581Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC598Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC608Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC618Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC628Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC631Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC641Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC658Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC668Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC672Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC682Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC693Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC701Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_ HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSM_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC718Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC024Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC11Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC21Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC31Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC448Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC510Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC61Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC73Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC83Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC91Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC101Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC119Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1210Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1310Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC141Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC151Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1648Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC171Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC181Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC1910Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC201Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC211Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC221Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC2310Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC241Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC251Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC261Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC271Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC2810Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC299Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC301Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC3110Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC3210Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC331Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC345Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC359Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC361Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC371Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC383Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC393Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4010Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC411Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC421Redundant
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4310Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4410Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC451Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC461Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC473Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC4810Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC493Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC508Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC511Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC521Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC538Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC548Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC552Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC562Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC573Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC581Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC598Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC608Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC618Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC628Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC631Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC641Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC658Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC668Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC672Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC682Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC693Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC701Parity
HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_ HC2_CBASS_EXPORT_ HC2_TO_RC_VBUSM_L1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC718Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_ RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC01Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_ RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC132Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_ RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC21Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_ RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC31Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_ RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC41Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_ RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC51Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_ RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC61Redundant
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_ RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC78Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_ RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC88Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_ RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC98Parity
HC2_CBASS_EXPORT_ RC_TO_HC2_VBUSP_L0_P2P_BRIDGE_EXPORT_ RC_TO_HC2_VBUSP_L0_BRIDGE_BUSECC108Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2051Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2126Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2220Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2318Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2418Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_251Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_261Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_271Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_281Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_291Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2101Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2111Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2123Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2133Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2148Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2158Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2168Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2178Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2183Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2193Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2201Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_22163Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_22262Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_22354Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_22426Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_22521Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_22619Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_22719Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2281Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2291Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2301Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2311Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2321Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2331Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2341Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2353Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2363Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2378Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2388Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2398Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2408Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2413Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2423Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2431Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_24463Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_24562Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_24654Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_24726Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_24821Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_24919Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_25019Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2511Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2521Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2531Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2541Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2551Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2561Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2571Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2583Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2593Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2608Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2618Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2628Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2638Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2643Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2653Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2661Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_26760Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_26859Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_26951Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_27026Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_27120Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_27218Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_27318Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2741Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2751Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2761Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2771Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2781Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2791Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2801Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2813Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2823Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2838Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2848Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2858Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2868Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2873Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2883Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2891Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_29060Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_29159Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_29251Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_29326Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_29420Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_29518Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_29618Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2971Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2981Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_2991Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21001Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21011Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21021Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21031Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21043Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21053Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21068Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21078Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21088Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21098Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21103Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21113Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21121Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_211360Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_211459Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_211551Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_211626Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_211720Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_211818Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_211918Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21201Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21211Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21221Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21231Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21241Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21251Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21261Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21273Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21283Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21298Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21308Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21318Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21328Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21333Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21343Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21351Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_213660Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_213759Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_213851Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_213926Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_214020Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_214118Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_214218Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21433Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21441Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_214560Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_214659Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_214751Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_214826Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_214920Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_215018Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_215118Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21523Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21531Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_215420Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_215526Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_215622Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_215720Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_215820Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21591Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21601Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21611Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21621Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21631Redundant
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21641Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_216532EDC
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_216632EDC
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_216732EDC
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_216832EDC
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21691Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21701Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_217148Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_217210Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21732Parity
HC2_CBASS_SCRM_128B_CLK1_SCR_ HC2_CBASS_SCRM_128B_CLK1_SCR_EDC_CTRL_BUSECC_21743Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_001Redundant
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_011Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_024Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0310Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0432EDC
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_051Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_062Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_072Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_081Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0930Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0102Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0117Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01210Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01312Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0144Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0153Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0161Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0171Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0181Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0191Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0207Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02110Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02210Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02312Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0244Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0253Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0261Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02710Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0283Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0293Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0301Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0311Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0321Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0331Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0345Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0351Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0361Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0371Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_03830Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0396Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0406Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0416Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0422Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_04310Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0448Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0457Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_046128Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0471Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0484Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_04912Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_05010Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_05148Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0521Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0531Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0541Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0551Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0561Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_05715Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_058128Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0597Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0607Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0617Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0627Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0637Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0647Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0657Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0667Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0677Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0687Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0697Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0707Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0717Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0727Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0737Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0747Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0757Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0767Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0777Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0787Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0797Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0807Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0817Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0827Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0837Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0847Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0857Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0867Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0877Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0887Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0897Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0907Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0917Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0927Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0937Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0947Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0957Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0967Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0977Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0987Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0997Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01007Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01017Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01027Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01037Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01047Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01057Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01067Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01077Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01087Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01097Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01107Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01117Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01127Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01137Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01147Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01157Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01167Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01177Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01187Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01197Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01207Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01217Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01227Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01237Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01247Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01257Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01267Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01277Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01287Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01297Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01307Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01317Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01327Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01337Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01347Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01357Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01367Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01377Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01387Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01397Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01407Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01417Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01427Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01437Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01447Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01457Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01467Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01477Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01487Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01497Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01507Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01517Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01527Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01537Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01547Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01557Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01567Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01577Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01587Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01597Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01607Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01617Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01627Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01637Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01647Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01657Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01667Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01677Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01687Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01697Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01707Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01717Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01727Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01737Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01747Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01757Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01767Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01777Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01787Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01797Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01807Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01817Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01827Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01837Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01847Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01857Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01867Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_018717Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_018817Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01891Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01901Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01911Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01921Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_019310Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01948Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01957Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0196128Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_019715Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_0198128Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_01997Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02007Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02017Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02027Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02037Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02047Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02057Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02067Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02077Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02087Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02097Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02107Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02117Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02127Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02137Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02147Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02157Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02167Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02177Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02187Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02197Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02207Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02217Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02227Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02237Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02247Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02257Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02267Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02277Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02287Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02297Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02307Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02317Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02327Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02337Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02347Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02357Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02367Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02377Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02387Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02397Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02407Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02417Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02427Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02437Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02447Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02457Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02467Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02477Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02487Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02497Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02507Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02517Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02527Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02537Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02547Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_02557Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_107Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_117Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_127Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_137Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_147Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_157Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_167Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_177Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_187Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_197Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1107Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1117Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1127Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1137Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1147Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1157Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1167Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1177Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1187Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1197Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1207Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1217Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1227Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1237Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1247Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1257Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1267Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1277Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1287Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1297Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1307Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1317Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1327Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1337Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1347Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1357Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1367Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1377Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1387Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1397Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1407Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1417Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1427Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1437Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1447Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1457Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1467Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1477Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1487Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1497Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1507Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1517Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1527Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1537Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1547Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1557Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1567Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1577Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1587Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1597Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1607Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1617Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1627Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1637Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1647Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1657Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1667Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1677Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1687Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1697Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1707Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_17150Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_17250Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_17312Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1744Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_17512Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_17610Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1773Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1781Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1798Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1804Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_18112Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_18212Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_18310Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_18410Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1851Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1861Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1871Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1881Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1895Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1903Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1913Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1923Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1931Parity
RC_TO_HC2_VBUSM_L0_STOG_3_EDC_CTRL_BUSECC_1948Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC01Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC132Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC21Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC31Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC41Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC51Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC61Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC78Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC88Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC98Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC108Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC111Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_1_CFG_BRIDGE_DST_BUSECC121Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC01Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC132Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC21Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC31Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC41Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC51Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC61Redundant
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC78Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC88Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC98Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC108Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC111Parity
HC2_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2HC2_0_CFG_BRIDGE_DST_BUSECC121Parity
MAIN_HC_ECC_AGGR_EDC_CTRL01Redundant
MAIN_HC_ECC_AGGR_EDC_CTRL132EDC
MAIN_HC_ECC_AGGR_EDC_CTRL21Parity
MAIN_HC_ECC_AGGR_EDC_CTRL310Parity
MAIN_HC_ECC_AGGR_EDC_CTRL44Parity
MAIN_HC_ECC_AGGR_EDC_CTRL53Parity