SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The clock slice creates the clock signal used by the SDRAM. The slice also disables the clock when instructed by the DDR controller through the DFI bus. When the clock is disabled, the CK pin drives low and the CKN drives high. Duty cycle correction is also applied in the memory clock slice.