ZHCSI27C April   2018  – October 2021 LM5036

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Voltage Start-Up Regulator
      2. 7.3.2  Undervoltage Lockout (UVLO)
      3. 7.3.3  Reference Regulator
      4. 7.3.4  Oscillator, Synchronized Input
      5. 7.3.5  Voltage-Mode Control
      6. 7.3.6  Primary-Side Gate Driver Outputs (LSG and HSG)
      7. 7.3.7  Half-Bridge PWM Scheme
      8. 7.3.8  Maximum Duty Cycle Operation
      9. 7.3.9  Pre-Biased Start-Up Process
        1. 7.3.9.1 Primary FETs Soft-Start Process
        2. 7.3.9.2 Synchronous Rectifier (SR) Soft-Start Process
      10. 7.3.10 Zero Duty Cycle Operation
      11. 7.3.11 Enhanced Cycle-by-Cycle Current Limiting with Pulse Matching
      12. 7.3.12 Reverse Current Protection
      13. 7.3.13 CBC Threshold Accuracy
      14. 7.3.14 Hiccup Mode Protection
      15. 7.3.15 Hiccup Mode Blanking
      16. 7.3.16 Over-Temperature Protection (OTP)
      17. 7.3.17 Over-Voltage / Latch (ON_OFF Pin)
      18. 7.3.18 Auxiliary Constant On-Time Control
      19. 7.3.19 Auxiliary On-Time Generator
      20. 7.3.20 Auxiliary Supply Current Limiting
      21. 7.3.21 Auxiliary Primary Output Capacitor Ripple
      22. 7.3.22 Auxiliary Ripple Configuration and Control
      23. 7.3.23 Asynchronous Mode Operation of Auxiliary Supply
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Input Transient Protection
        3. 8.2.2.3  Level-Shift Detection Circuit
        4. 8.2.2.4  Applications with VIN > 100-V
        5. 8.2.2.5  Applications without Pre-Biased Start-Up Requirement
        6. 8.2.2.6  UVLO Voltage Divider Selection
        7. 8.2.2.7  Over Voltage, Latch (ON_OFF Pin) Voltage Divider Selection
        8. 8.2.2.8  SS Capacitor
        9. 8.2.2.9  SSSR Capacitor
        10. 8.2.2.10 Half-Bridge Power Stage Design
        11. 8.2.2.11 Current Limit
        12. 8.2.2.12 Auxiliary Transformer
        13. 8.2.2.13 Auxiliary Feedback Resistors
        14. 8.2.2.14 RON Resistor
        15. 8.2.2.15 VIN Pin Capacitor
        16. 8.2.2.16 Auxiliary Primary Output Capacitor
        17. 8.2.2.17 Auxiliary Secondary Output Capacitor
        18. 8.2.2.18 Auxiliary Feedback Ripple Circuit
        19. 8.2.2.19 Auxiliary Secondary Diode
        20. 8.2.2.20 VCC Diode
        21. 8.2.2.21 Opto-Coupler Interface
        22. 8.2.2.22 Full-Bridge Converter Applications
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
        1. 11.2.1.1 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.3.14 Hiccup Mode Protection

A block diagram of the hiccup mode function is shown in Figure 7-17. Both the repetitive CBC and negative current limit events will trigger hiccup mode operation in LM5036 device.

GUID-A8D89778-1C5D-4677-B070-C905BBCDF8DE-low.gifFigure 7-17 Hiccup Mode Circuitry

The device charges the hiccup restart capacitor with a current source IRES-SRC1 (15-µA typical) during CBC operation. The hiccup mode is activated when VRES exceeds 1 V. During hiccup mode operation, the SS and SSSR capacitors are fully discharged and the half-bridge converter remains off for a period of time (tHIC) before a new soft-start sequence is initiated.

GUID-A3F355B0-F979-4FEE-80A7-D1C7614E6BE3-low.gifFigure 7-18 Hiccup Mode Activated By Continuous CBC Operation

Use Equation 26 to calculate the duration of CBC operation before entering the hiccup mode.

Equation 26. GUID-A89795D0-4CB5-4455-8DF0-B6413E5B15E6-low.gif

where

  • CRES is the value of the hiccup capacitor

After the RES pin reaches 1.0-V, current source IRES-SRC1 (15-μA typical) is turned off and current source IRES-SRC2 (30-μA typical) is turned on which charges the RES capacitor to 4-V. Then current source IRES-DIS2 (5-μA typical) is enabled which discharges the RES capacitor to 2-V.

Use Equation 27 to calculate the hiccup mode off-time.

Equation 27. GUID-863AC587-5845-475C-A1FD-675B78F24944-low.gif

In addition to the repetitive CBC current limit condition, the device also enters hiccup mode if the SSSR capacitor is clamped for eight times due to repetitive negative current limit condition. The operating pattern of the hiccup mode activated by the negative current limit is similar to that activated by CBC current limit. The only difference is that at the beginning of the hiccup mode operation the RES capacitor is charged with current source IRES-SRC2 when activated by negative current limit as illustrated in Figure 7-19 whereas the RES capacitor is charged with current source IRES-SRC1 when activated by CBC current limit condition.

GUID-3884774B-6ACF-46B4-8356-FC14BA754FDD-low.gif
(1) SSSR capacitor clamp event counter
Figure 7-19 Hiccup Mode Activated By Repetitive Negative OCP Condition

Once the hiccup off-timer expires, the SSSR capacitor clamp event counter will be reset. If SSSR capacitor gets clamped for less than eight times before the SSSR capacitor voltage is fully ramped up to its maximum value, the SSSR capacitor clamp event counter will also be reset. This is because the fact that SSSR capacitor voltage is able to fully ramp up to its maximum value indicates that repetitive negative current limit condition no longer exists.