ZHCSI27C April 2018 – October 2021 LM5036
PRODUCTION DATA
The SSSR capacitor value determines the rate at which the pulse width of the SRs of the half-bridge converter increases. To achieve a monotonic start-up for the output voltage, the optimum SSSR capacitor value satisfies the following two conditions:
A general rule is to maintain the control loop bandwidth of the half-bridge converter above 1 kHz. With a slow control loop bandwidth, the output voltage needs to drop at least 25% from the regulation set-point during the restart time period where the SS pin voltage rises from 0 V to VSSSecEn (2.06-V typical) and then the secondary-side reference VREF rises to 75% of regulation set-point. To satisfy the first condition above, maintain the rise time of the SSSR capacitor voltage to less than 25% of the rise time of the output voltage, as described in Equation 53.
where
Use the SSSR capacitor value calculated from Equation 53 as a starting point. Fine-tuning may be needed based on the actual control loop design and other specific design requirements such as pre-bias conditions and loading profile.