ZHCSA85F August   2012  – February 2019 DLPC410

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化应用
  4. 修订历史记录
  5. 说明 (续)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Timing Requirements
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 Binary Pattern Data Path
        1. 8.3.1.1  DIN_A, DIN_B, DIN_C, DIN_D Input Data Buses
        2. 8.3.1.2  DCLKIN Input Clocks
        3. 8.3.1.3  DVALID Input Signals
        4. 8.3.1.4  DOUT_A, DOUT_B, DOUT_C, DOUT_D Output Data Buses
        5. 8.3.1.5  DCLKOUT Output Clocks
        6. 8.3.1.6  SCTRL Output Signals
        7. 8.3.1.7  Supported DMD Bus Sizes
        8. 8.3.1.8  Row Cycle definition
        9. 8.3.1.9  DLP9500 and DLP9500UV Input Data Formatting
        10. 8.3.1.10 DLP7000 and DLP7000UV Input Data Bus
        11. 8.3.1.11 DLP650LNIR Input Data Bus
      2. 8.3.2 Data Bus Operations
        1. 8.3.2.1 Row Addressing
        2. 8.3.2.2 Single Row Write Operation
        3. 8.3.2.3 No-Op Row Cycle Description
      3. 8.3.3 DMD Block Operations
        1. 8.3.3.1 Mirror Clocking Pulse (MCP)
        2. 8.3.3.2 Reset Active (RST_ACTIVE)
        3. 8.3.3.3 DMD Block Control Signals
          1. 8.3.3.3.1 Block Mode - BLK_MD1:0)
          2. 8.3.3.3.2 Block Address - BLK_AD(3:0)
          3. 8.3.3.3.3 Reset 2 Blocks - RST2BLK
        4. 8.3.3.4 DMD Block Operations
          1. 8.3.3.4.1 Global Reset (MCP) Consideration
      4. 8.3.4 Other Data Control Inputs
        1. 8.3.4.1 Complement Data
        2. 8.3.4.2 North/South Flip
      5. 8.3.5 Miscellaneous Control Inputs
        1. 8.3.5.1 ARST
        2. 8.3.5.2 CLKIN_R
        3. 8.3.5.3 DMD_A_RESET
        4. 8.3.5.4 Watchdog Timer Enable (WDT_ENABLE)
      6. 8.3.6 Miscellaneous Status Outputs
        1. 8.3.6.1 INIT_ACTIVE
        2. 8.3.6.2 DMD_Type(3:0)
        3. 8.3.6.3 DDC_VERSION(3:0)
        4. 8.3.6.4 LED0
        5. 8.3.6.5 LED1
        6. 8.3.6.6 DLPA200 Control Signals
        7. 8.3.6.7 ECM2M_TP_ (31:0)
    4. 8.4 Device Functional Modes
      1. 8.4.1 DLPC410 Initialization and Training
        1. 8.4.1.1 Initialization
        2. 8.4.1.2 input Data Interface (DIN) Training Pattern
      2. 8.4.2 DLPC410 Operational Modes
        1. 8.4.2.1 Single Block Mode
        2. 8.4.2.2 Single Block Phased Mode
        3. 8.4.2.3 Dual Block Mode
        4. 8.4.2.4 Quad Block Mode
        5. 8.4.2.5 Global Mode
        6. 8.4.2.6 DMD Park Mode
        7. 8.4.2.7 DMD Idle Mode
      3. 8.4.3 LOAD4 Functionality (enabled with DLPR410A)
        1. 8.4.3.1 Enabling LOAD4
        2. 8.4.3.2 Loading Data with LOAD4
        3. 8.4.3.3 Row Mapping with LOAD4
        4. 8.4.3.4 Using Block Clear with LOAD4
        5. 8.4.3.5 Timing Requirements for LOAD4
        6. 8.4.3.6 Global Binary Pattern Rate increases using LOAD4
        7. 8.4.3.7 Special LOAD4 considerations
    5. 8.5 Programming
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Description
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Setup
      1. 9.3.1 Debugging Guidelines
      2. 9.3.2 Initialization
        1. 9.3.2.1 Calibration
        2. 9.3.2.2 DLPA200 Number 1 Initialization
        3. 9.3.2.3 DMD Initialization
          1. 9.3.2.3.1 DMD Device ID Check
          2. 9.3.2.3.2 DMD Device OK
        4. 9.3.2.4 DLPA200 Number 2 Initialization
        5. 9.3.2.5 Command Sequence Initialization
      3. 9.3.3 Image Display Issues
        1. 9.3.3.1 Present Data to DLPC410
        2. 9.3.3.2 Load Data to DMD
        3. 9.3.3.3 Mirror Clocking Pulse
  10. 10Power Supply Recommendations
    1. 10.1 Power Down Operation
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
      4. 11.1.4 PCB Layout Guidelines
        1. 11.1.4.1 DMD Interface
          1. 11.1.4.1.1 Trace Length Matching
        2. 11.1.4.2 DLPC410 DMD Decoupling
          1. 11.1.4.2.1 Decoupling Capacitors
        3. 11.1.4.3 VCC and VCC2
        4. 11.1.4.4 DMD Layout
        5. 11.1.4.5 DLPA200
    2. 11.2 Layout Example
    3. 11.3 DLPC410 Chipset Connections
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 器件标记
      2. 12.1.2 器件命名规则
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

DLP7000 and DLP7000UV Input Data Bus

Figure 8 details one row cycle of input data formatting for the DLP7000 and DLP7000UV DMDs. For brevity, only two data bits of both 16 bit data bus (A/B) signals are shown, but there is enough information presented to allow extrapolation to data bus signals not shown.


Table 7 and Table 8 show how each pixel of the DLP7000 and DLP7000UV DMDs maps to individual data bus inputs and input clock edges within each row load operation.

NOTE

In the following charts, for readability purposes input buses DIN_A, DIN_B are abbreviated as D_A, D_B. DCLKIN has been shortened to DCLK.

DLPC410 XGA_ip_data_bus_lps024.gifFigure 8. DLP7000 / DLP7000UV 2XLVDS DMD Input Data Bus

Table 7. DLP7000 / DLP7000UV 2XLVDS DMD Data Pixel Mapping D_A(15:0)

DCLK EDGE D_A(0) D_A(1) D_A(2) D_A(3) D_A(4) D_A(5) D_A(6) D_A(7) D_A(8) D_A(9) D_A(10) D_A(11) D_A(12) D_A(13) D_A(14) D_A(15)
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
2 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
3 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
4 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143
5 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175
6 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207
7 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239
8 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271
9 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303
10 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335
11 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367
12 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399
13 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431
14 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463
15 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495
16 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527
17 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559
18 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591
19 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623
20 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655
21 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687
22 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719
23 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751
24 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783
25 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815
26 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847
27 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879
28 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911
29 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943
30 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975
31 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007

Table 8. DLP7000 / DLP7000UV 2XLVDS DMD Data Pixel Mapping D_B(15:0)

DCLK EDGE D_B(0) D_B(1) D_B(2) D_B(3) D_B(4) D_B(5) D_B(6) D_B(7) D_B(8) D_B(9) D_B(10) D_B(11) D_B(12) D_B(13) D_B(14) D_B(15)
0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
2 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
3 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
4 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159
5 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191
6 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223
7 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
8 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287
9 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319
10 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351
11 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383
12 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415
13 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447
14 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479
15 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511
16 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543
17 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575
18 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607
19 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639
20 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671
21 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703
22 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735
23 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767
24 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799
25 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831
26 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863
27 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895
28 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927
29 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959
30 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991
31 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023