ZHCSA85F August 2012 – February 2019 DLPC410
The SCTRL signal is a differential output signal to the DMD which provides DMD control information. There are four SCTRL differential pair signals, one for each bus (A/B/C/D). The control information is generated internally to the DLPC410 and is specific to the connected DMD. Data should be synchronous and edge aligned with the output clocks for each specific data bus (A, B, C, or D). Depending on the design, skewing the clock to SCTRL relationship may cause a problem. For timing constraints for the output data clock to the SCTRL signals, refer to Timing Requirements.