ZHCSA85F August   2012  – February 2019 DLPC410

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 Binary Pattern Data Path
        1. 8.3.1.1  DIN_A, DIN_B, DIN_C, DIN_D Input Data Buses
        2. 8.3.1.2  DCLKIN Input Clocks
        3. 8.3.1.3  DVALID Input Signals
        4. 8.3.1.4  DOUT_A, DOUT_B, DOUT_C, DOUT_D Output Data Buses
        5. 8.3.1.5  DCLKOUT Output Clocks
        6. 8.3.1.6  SCTRL Output Signals
        7. 8.3.1.7  Supported DMD Bus Sizes
        8. 8.3.1.8  Row Cycle definition
        9. 8.3.1.9  DLP9500 and DLP9500UV Input Data Formatting
        10. 8.3.1.10 DLP7000 and DLP7000UV Input Data Bus
        11. 8.3.1.11 DLP650LNIR Input Data Bus
      2. 8.3.2 Data Bus Operations
        1. 8.3.2.1 Row Addressing
        2. 8.3.2.2 Single Row Write Operation
        3. 8.3.2.3 No-Op Row Cycle Description
      3. 8.3.3 DMD Block Operations
        1. 8.3.3.1 Mirror Clocking Pulse (MCP)
        2. 8.3.3.2 Reset Active (RST_ACTIVE)
        3. 8.3.3.3 DMD Block Control Signals
          1. 8.3.3.3.1 Block Mode - BLK_MD1:0)
          2. 8.3.3.3.2 Block Address - BLK_AD(3:0)
          3. 8.3.3.3.3 Reset 2 Blocks - RST2BLK
        4. 8.3.3.4 DMD Block Operations
          1. 8.3.3.4.1 Global Reset (MCP) Consideration
      4. 8.3.4 Other Data Control Inputs
        1. 8.3.4.1 Complement Data
        2. 8.3.4.2 North/South Flip
      5. 8.3.5 Miscellaneous Control Inputs
        1. 8.3.5.1 ARST
        2. 8.3.5.2 CLKIN_R
        3. 8.3.5.3 DMD_A_RESET
        4. 8.3.5.4 Watchdog Timer Enable (WDT_ENABLE)
      6. 8.3.6 Miscellaneous Status Outputs
        1. 8.3.6.1 INIT_ACTIVE
        2. 8.3.6.2 DMD_Type(3:0)
        3. 8.3.6.3 DDC_VERSION(3:0)
        4. 8.3.6.4 LED0
        5. 8.3.6.5 LED1
        6. 8.3.6.6 DLPA200 Control Signals
        7. 8.3.6.7 ECM2M_TP_ (31:0)
    4. 8.4 Device Functional Modes
      1. 8.4.1 DLPC410 Initialization and Training
        1. 8.4.1.1 Initialization
        2. 8.4.1.2 input Data Interface (DIN) Training Pattern
      2. 8.4.2 DLPC410 Operational Modes
        1. 8.4.2.1 Single Block Mode
        2. 8.4.2.2 Single Block Phased Mode
        3. 8.4.2.3 Dual Block Mode
        4. 8.4.2.4 Quad Block Mode
        5. 8.4.2.5 Global Mode
        6. 8.4.2.6 DMD Park Mode
        7. 8.4.2.7 DMD Idle Mode
      3. 8.4.3 LOAD4 Functionality (enabled with DLPR410A)
        1. 8.4.3.1 Enabling LOAD4
        2. 8.4.3.2 Loading Data with LOAD4
        3. 8.4.3.3 Row Mapping with LOAD4
        4. 8.4.3.4 Using Block Clear with LOAD4
        5. 8.4.3.5 Timing Requirements for LOAD4
        6. 8.4.3.6 Global Binary Pattern Rate increases using LOAD4
        7. 8.4.3.7 Special LOAD4 considerations
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Description
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Setup
      1. 9.3.1 Debugging Guidelines
      2. 9.3.2 Initialization
        1. 9.3.2.1 Calibration
        2. 9.3.2.2 DLPA200 Number 1 Initialization
        3. 9.3.2.3 DMD Initialization
          1. 9.3.2.3.1 DMD Device ID Check
          2. 9.3.2.3.2 DMD Device OK
        4. 9.3.2.4 DLPA200 Number 2 Initialization
        5. 9.3.2.5 Command Sequence Initialization
      3. 9.3.3 Image Display Issues
        1. 9.3.3.1 Present Data to DLPC410
        2. 9.3.3.2 Load Data to DMD
        3. 9.3.3.3 Mirror Clocking Pulse
  10. 10Power Supply Recommendations
    1. 10.1 Power Down Operation
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
      4. 11.1.4 PCB Layout Guidelines
        1. 11.1.4.1 DMD Interface
          1. 11.1.4.1.1 Trace Length Matching
        2. 11.1.4.2 DLPC410 DMD Decoupling
          1. 11.1.4.2.1 Decoupling Capacitors
        3. 11.1.4.3 VCC and VCC2
        4. 11.1.4.4 DMD Layout
        5. 11.1.4.5 DLPA200
    2. 11.2 Layout Example
    3. 11.3 DLPC410 Chipset Connections
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 器件标记
      2. 12.1.2 器件命名规则
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
  • DLP|676
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.1.11 DLP650LNIR Input Data Bus

Figure 9 details one row cycle of input data formatting for the DLP650LNIR DMD. For brevity, only two data bits of both 8 bit data bus (A/B) signals are shown, but there is enough information presented to allow extrapolation to data bus signals not shown.


Table 9 and Table 10 show how each pixel of the DLP650LNIR DMD maps to individual data bus inputs and input clock edges within each row load operation.

NOTE

In the following charts, for readability purposes input buses DIN_A, DIN_B are abbreviated as D_A, D_B. DCLKIN has been shortened to DCLK.

Since showing the entire 40 clock row cycle would make this chart unreadable, the chart has been broken in the middle. However, there is enough information available to allow extrapolation of the missing data.

DLPC410 650LNIR-C410-dataload.gifFigure 9. DLP650LNIR 2xLVDS DMD Input Data Bus

Table 9. DLP650LNIR 2xLVDS DMD Data Pixel Mapping D_A(15,13,11,9,7,5,3,1)

DCLK EDGE D_A(1) D_A(3) D_A(5) D_A(7 D_A(9) D_A(11) D_A(13) D_A(15)
0 0 2 4 6 8 10 12 14
1 32 34 36 38 40 42 44 46
2 64 66 68 70 72 74 76 78
3 96 98 100 102 104 106 108 110
4 1 3 5 7 9 11 13 15
5 33 35 37 39 41 43 45 47
6 65 67 69 71 73 75 77 79
7 97 99 101 103 105 107 109 111
8 128 130 132 134 136 138 140 142
9 160 162 164 166 168 170 172 174
10 192 194 196 198 200 202 204 206
11 224 226 228 230 232 234 236 238
12 129 131 133 135 137 139 141 143
13 161 163 165 167 169 171 173 175
14 193 195 197 199 201 203 205 207
15 225 227 229 231 233 235 237 239
16 256 258 260 262 264 266 268 270
17 288 290 292 294 296 298 300 302
18 320 322 324 326 328 330 332 334
19 352 354 356 358 360 362 364 366
20 257 259 261 263 265 267 269 271
21 289 291 293 295 297 299 301 303
22 321 323 325 327 329 331 333 335
23 353 355 357 359 361 363 365 367
24 384 386 388 390 392 394 396 398
25 416 418 420 422 424 426 428 430
26 448 450 452 454 456 458 460 462
27 480 482 484 486 488 490 492 494
28 385 387 389 391 393 395 397 399
29 417 419 421 423 425 427 429 431
30 449 451 453 455 457 459 461 463
31 481 483 485 487 489 491 493 495
32 512 514 516 518 520 522 524 526
33 544 546 548 550 552 554 556 558
34 576 578 580 582 584 586 588 590
35 608 610 612 614 616 618 620 622
36 513 515 517 519 521 523 525 527
37 545 547 549 551 553 555 557 559
38 577 579 581 583 585 587 589 591
39 609 611 613 615 617 619 621 623
40 640 642 644 646 648 650 652 654
41 672 674 676 678 680 682 684 686
42 704 706 708 710 712 714 716 718
43 736 738 740 742 744 746 748 750
44 641 643 645 647 649 651 653 655
45 673 675 677 679 681 683 685 687
46 705 707 709 711 713 715 717 719
47 737 739 741 743 745 747 749 751
48 768 770 772 774 776 778 780 782
49 800 802 804 806 808 810 812 814
50 832 834 836 838 840 842 844 846
51 864 866 868 870 872 874 876 878
52 769 771 773 775 777 779 781 783
53 801 803 805 807 809 811 813 815
54 833 835 837 839 841 843 845 847
55 865 867 869 871 873 875 877 879
56 896 898 900 902 904 906 908 910
57 928 930 832 934 936 938 940 942
58 960 962 964 966 968 970 972 974
59 992 994 996 998 1000 1002 1004 1006
60 897 899 901 903 905 907 909 911
61 929 931 933 935 937 939 941 943
62 961 963 965 967 969 971 973 975
63 993 995 997 999 1001 1003 1005 1007
64 1024 1026 1028 1030 1032 1034 1036 1038
65 1056 1058 1060 1062 1064 1066 1068 1070
66 1088 1090 1092 1094 1096 1098 1100 1102
67 1120 1122 1124 1126 1128 1130 1132 1134
68 1025 1027 1029 1031 1033 1035 1037 1039
69 1057 1059 1061 1063 1065 1067 1069 1071
70 1089 1091 1093 1095 1097 1099 1101 1103
71 1121 1123 1125 1127 1129 1131 1133 1135
72 1152 1154 1156 1158 1160 1162 1164 1166
73 1184 1186 1188 1190 1192 1194 1196 1198
74 1216 1218 1220 1222 1224 1226 1228 1230
75 1248 1250 1252 1254 1256 1258 1260 1262
76 1153 1155 1157 1159 1161 1163 1165 1167
77 1185 1187 1189 1191 1193 1195 1197 1199
78 1217 1219 1221 1223 1225 1227 1229 1231
79 1249 1251 1253 1255 1257 1259 1261 1263

Table 10. DLP650LNIR 2xLVDS DMD Data Pixel Mapping D_B(15,13,11,9,7,5,3,1)

DCLK EDGE D_B(1) D_B(3) D_B(5) D_B(7) D_B(9) D_B(11) D_B(13) D_B(15)
0 16 18 20 22 24 26 28 30
1 48 50 52 54 56 58 60 62
2 80 82 84 86 88 90 92 94
3 112 114 116 118 120 122 124 126
4 17 19 21 23 25 27 29 31
5 49 51 53 55 57 59 61 63
6 81 83 85 87 89 91 93 95
7 113 115 117 119 121 123 125 127
8 144 146 148 150 152 154 156 158
9 176 178 180 182 184 186 188 190
10 208 210 212 214 216 218 220 222
11 240 242 244 246 248 250 252 254
12 145 147 149 151 153 155 157 159
13 177 179 181 183 185 187 189 191
14 209 211 213 215 217 219 221 223
15 241 243 245 247 249 251 253 255
16 272 274 276 278 280 282 284 286
17 304 306 308 310 312 314 316 318
18 336 338 340 342 344 346 348 350
19 368 370 372 374 376 378 380 382
20 273 275 277 279 281 283 285 287
21 305 307 309 311 313 315 317 319
22 337 339 341 343 345 347 349 351
23 369 371 373 375 377 379 381 383
24 400 402 404 406 408 410 412 414
25 432 434 436 438 440 442 444 446
26 464 466 468 470 472 474 476 478
27 496 498 500 502 504 506 508 510
28 401 403 405 407 409 411 413 415
29 433 435 437 439 441 443 445 447
30 465 467 469 471 473 475 477 479
31 497 499 501 503 505 507 509 511
32 528 530 532 534 536 538 540 542
33 560 562 564 566 568 570 572 574
34 592 594 596 598 600 602 604 606
35 624 626 628 630 632 634 636 638
36 529 531 533 535 537 539 541 543
37 561 563 565 567 569 571 573 575
38 593 595 597 599 601 603 605 607
39 625 627 629 631 633 635 637 639
40 656 658 660 662 664 666 668 670
41 688 690 692 694 696 698 700 702
42 720 722 724 726 728 730 732 734
43 752 754 756 758 760 762 764 766
44 657 659 661 663 665 667 669 671
45 689 691 693 695 697 699 701 703
46 721 723 725 727 729 731 733 735
47 753 755 757 759 761 763 765 767
48 784 786 788 790 792 794 796 798
49 816 818 820 822 824 826 828 830
50 848 850 852 854 856 858 860 862
51 880 882 884 886 888 890 892 894
52 785 787 789 791 793 795 797 799
53 817 819 821 823 825 827 829 831
54 849 851 853 855 857 859 861 863
55 881 883 885 887 889 891 893 895
56 912 914 916 918 920 922 924 926
57 944 946 948 950 952 954 956 958
58 976 978 980 982 984 986 988 990
59 1008 1010 1012 1014 1016 1018 1020 1022
60 913 915 917 919 921 923 925 927
61 945 947 949 951 953 955 957 959
62 977 979 981 983 985 987 989 991
63 1009 1011 1013 1015 1017 1019 1021 1023
64 1040 1042 1044 1046 1048 1050 1052 1054
65 1072 1074 1076 1078 1080 1082 1084 1086
66 1104 1106 1108 1110 1112 1114 1116 1118
67 1136 1138 1140 1142 1144 1146 1148 1150
68 1041 1043 1045 1047 1049 1051 1053 1055
69 1073 1075 1077 1079 1081 1083 1085 1087
70 1105 1107 1109 1111 1113 1115 1117 1119
71 1137 1139 1141 1143 1145 1147 1149 1151
72 1168 1170 1172 1174 1176 1178 1180 1182
73 1200 1202 1204 1206 1208 1210 1212 1214
74 1232 1234 1236 1238 1240 1242 1244 1246
75 1264 1266 1268 1270 1272 1274 1276 1278
76 1169 1171 1173 1175 1177 1179 1181 1183
77 1201 1203 1205 1207 1209 1211 1213 1215
78 1233 1235 1237 1239 1241 1243 1245 1247
79 1265 1267 1269 1271 1273 1275 1277 1279