ZHCSA85F August 2012 – February 2019 DLPC410
A Row Cycle relates to specific number of input data clocks it takes for the customer to send one row of input binary pattern data to one row of the DMD. DVALID starts the Row Cycle by transitioning to an active (logic '1') state. The row cycle ends after the appropriate number of clock cycles per row are applied. Any input data on the DIN input data buses should be appropriately provided during the Row Cycle. Table 2 shows the number of input data clocks needing to populate one row of the DMD using the number of data lines identified in the table. Other Row and Block related signals are captured at the start of a row cycle and will be discussed later.
There is also a unique row cycle called a No-Op Row Cycle which does not provide any valid input data nor any valid block command. It is typically used to do nothing except provide the DLPC410 and DMD time to perform internal actions already in process. The No-Op Row Cycle is discussed in No-Op Row Cycle Description.