ZHCSA85F August 2012 – February 2019 DLPC410
DCLKOUT is the differential output clock for each DLPC410 output data bus. There are four output data clocks, one for each bus (A/B/C/D) to the DMD. DCLKOUT is a 400 MHz clock to the DMD which should be synchronous and edge aligned with all data and control signals for that specific bus (A, B, C, or D). Depending on the design, skewing the clock to data relationship may cause a problem. For timing constraints for the output data clocks to either the output data and/or SCTRL signals, refer to Timing Requirements.