ZHCSA85F August   2012  – February 2019 DLPC410

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化应用
  4. 修订历史记录
  5. 说明 (续)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Timing Requirements
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 Binary Pattern Data Path
        1. 8.3.1.1  DIN_A, DIN_B, DIN_C, DIN_D Input Data Buses
        2. 8.3.1.2  DCLKIN Input Clocks
        3. 8.3.1.3  DVALID Input Signals
        4. 8.3.1.4  DOUT_A, DOUT_B, DOUT_C, DOUT_D Output Data Buses
        5. 8.3.1.5  DCLKOUT Output Clocks
        6. 8.3.1.6  SCTRL Output Signals
        7. 8.3.1.7  Supported DMD Bus Sizes
        8. 8.3.1.8  Row Cycle definition
        9. 8.3.1.9  DLP9500 and DLP9500UV Input Data Formatting
        10. 8.3.1.10 DLP7000 and DLP7000UV Input Data Bus
        11. 8.3.1.11 DLP650LNIR Input Data Bus
      2. 8.3.2 Data Bus Operations
        1. 8.3.2.1 Row Addressing
        2. 8.3.2.2 Single Row Write Operation
        3. 8.3.2.3 No-Op Row Cycle Description
      3. 8.3.3 DMD Block Operations
        1. 8.3.3.1 Mirror Clocking Pulse (MCP)
        2. 8.3.3.2 Reset Active (RST_ACTIVE)
        3. 8.3.3.3 DMD Block Control Signals
          1. 8.3.3.3.1 Block Mode - BLK_MD1:0)
          2. 8.3.3.3.2 Block Address - BLK_AD(3:0)
          3. 8.3.3.3.3 Reset 2 Blocks - RST2BLK
        4. 8.3.3.4 DMD Block Operations
          1. 8.3.3.4.1 Global Reset (MCP) Consideration
      4. 8.3.4 Other Data Control Inputs
        1. 8.3.4.1 Complement Data
        2. 8.3.4.2 North/South Flip
      5. 8.3.5 Miscellaneous Control Inputs
        1. 8.3.5.1 ARST
        2. 8.3.5.2 CLKIN_R
        3. 8.3.5.3 DMD_A_RESET
        4. 8.3.5.4 Watchdog Timer Enable (WDT_ENABLE)
      6. 8.3.6 Miscellaneous Status Outputs
        1. 8.3.6.1 INIT_ACTIVE
        2. 8.3.6.2 DMD_Type(3:0)
        3. 8.3.6.3 DDC_VERSION(3:0)
        4. 8.3.6.4 LED0
        5. 8.3.6.5 LED1
        6. 8.3.6.6 DLPA200 Control Signals
        7. 8.3.6.7 ECM2M_TP_ (31:0)
    4. 8.4 Device Functional Modes
      1. 8.4.1 DLPC410 Initialization and Training
        1. 8.4.1.1 Initialization
        2. 8.4.1.2 input Data Interface (DIN) Training Pattern
      2. 8.4.2 DLPC410 Operational Modes
        1. 8.4.2.1 Single Block Mode
        2. 8.4.2.2 Single Block Phased Mode
        3. 8.4.2.3 Dual Block Mode
        4. 8.4.2.4 Quad Block Mode
        5. 8.4.2.5 Global Mode
        6. 8.4.2.6 DMD Park Mode
        7. 8.4.2.7 DMD Idle Mode
      3. 8.4.3 LOAD4 Functionality (enabled with DLPR410A)
        1. 8.4.3.1 Enabling LOAD4
        2. 8.4.3.2 Loading Data with LOAD4
        3. 8.4.3.3 Row Mapping with LOAD4
        4. 8.4.3.4 Using Block Clear with LOAD4
        5. 8.4.3.5 Timing Requirements for LOAD4
        6. 8.4.3.6 Global Binary Pattern Rate increases using LOAD4
        7. 8.4.3.7 Special LOAD4 considerations
    5. 8.5 Programming
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Description
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Setup
      1. 9.3.1 Debugging Guidelines
      2. 9.3.2 Initialization
        1. 9.3.2.1 Calibration
        2. 9.3.2.2 DLPA200 Number 1 Initialization
        3. 9.3.2.3 DMD Initialization
          1. 9.3.2.3.1 DMD Device ID Check
          2. 9.3.2.3.2 DMD Device OK
        4. 9.3.2.4 DLPA200 Number 2 Initialization
        5. 9.3.2.5 Command Sequence Initialization
      3. 9.3.3 Image Display Issues
        1. 9.3.3.1 Present Data to DLPC410
        2. 9.3.3.2 Load Data to DMD
        3. 9.3.3.3 Mirror Clocking Pulse
  10. 10Power Supply Recommendations
    1. 10.1 Power Down Operation
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 Fiducials
      4. 11.1.4 PCB Layout Guidelines
        1. 11.1.4.1 DMD Interface
          1. 11.1.4.1.1 Trace Length Matching
        2. 11.1.4.2 DLPC410 DMD Decoupling
          1. 11.1.4.2.1 Decoupling Capacitors
        3. 11.1.4.3 VCC and VCC2
        4. 11.1.4.4 DMD Layout
        5. 11.1.4.5 DLPA200
    2. 11.2 Layout Example
    3. 11.3 DLPC410 Chipset Connections
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 器件标记
      2. 12.1.2 器件命名规则
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Row Addressing

The DIN (input data), DCLKIN (input data clock), and DVALID (data valid) signals enable the DLPC410 to capture one row of customer input data and send that data to the DMD. For the DMD to know specifically to which row the data will be applied, the ROW_MD(1:0) (row mode), the ROW_AD(10:0) (row address), and the NS_FLIP (North/South Flip) signal inputs must be presented to the DLPC410 inputs during each row cycle. Table 11 shows the number of rows for each DMD supported by the DLPC410.

Table 11. DMD Row and Columns

TYPE COLUMNS ROWS CLOCKS PER ROW NO. OF DATA LINES
DLP650LNIR DMD 1280 800 40 16
DLP7000 and DLP7000UV DMDs 1024 768 16 32
DLP9500 and DLP9500UV DMDs 1920 (2048)(1) 1080 16 64
The DLP9500 and DLP9500UV DMDs have 2048 memory cells per row . There are 64 bits at the beginning of each row and 64 bits at the end of each row which do not have corresponding DMD micromirrors. These 128 memory cells must be loaded with data but the data content can be arbitrary and will not affect the 1920 physical micromirrors within that row.

DMD data is loaded into the DMD SRAM pixels one row of data at a time. The DLP9500 and DLP9500UV require pattern data input to all four input data buses (A,B,C,D) while the DLP650LNIR, DLP7000 and DLP7000UV require pattern data to be input to two input data buses (A,B). The DLP650LNIR uses only the odd data bus pins of input buses A and B. The DMD input data buses are provided by the following DLPC410 outputs:

  • DDC_DCLKOUT - high speed 2xLVDS data clock out to DMD
  • SCTRL - high speed control bus to DMD
  • DDC_DOUT[X:Y] - 2xLVDS data bus where X and Y depend on the DMD.
These signals are all output from the DLPC410 and are listed in Pin Configuration and Functions. Data and control from the DLPC410 are clocked into the DMD on both the rising and falling edges of the DDR data clocks: DDC_DCLKOUT_[A, B] for the 2 input bus DMDs and DDC_DCLKOUT_[A, B, C, D] for the 4 input bus DMDs. Data loading does not cause mirror state changes - mirrors transition to the next state only when a Mirror Clocking Pulse (Reset) operation is performed.

The row load length in clocks can be determined by the following equation: number row clocks = number of pixels per row / (total data buses bit width × 2 edges per clock). The "2 edges per clock" in the denominator is a direct results of the Dual Data Rate (DDR) nature of the DMD input data bus. This equation yields the results shown in Table 11


The DMD incorporates single row write operations using a row address counter that has different modes of operation. These modes are dependent on the state of the ROW_MD, ROW_AD, and NS_FLIP input signals. As shown in Table 12, ROW_MD(1:0) determines the row mode for a given Row Cycle, and, when ROW_MD = "10", then ROW_AD(10:0) selects the customer supplied single row address. ROW_MD and ROW_AD must be asserted and deasserted synchronously with DVALID and must be valid synchronous to the beginning of the data as shown in Figure 10. If only one specific mode will be utilized in a customer system application, it is certainly acceptable to leave these values at their same desired input levels for as long as desired.

Row address orientation depends on the North/South Flip Flag (NS_FLIP) input to the DLPC410. This input controls if the DMD starting row address starts at the top of the DMD (Row 0) and increments downward, or from the bottom of the DMD (last row) and decrements upward.

The row address counter does not automatically wrap-around when using the increment row address pointer instructions. For example, after the final row is addressed, the row address pointer must be set to row 0.

Table 12. Row Modes and Row Addresses

ROW_MD(1:0) ROW_AD(10:0)(1) NS_FLIP(2) ACTION
"00" "xxxxxxxxxxx" "x" Row No-Op (No data write)
"01" "xxxxxxxxxxx" 0 Increment internal row address by '1' - write concurrent data into that row
"01" "xxxxxxxxxxx" 1 Decrement internal row address by '1' - write concurrent data into that row
"10" ROW_AD(10:0) "x" Set Random row address as specified on ROW_AD(10:0) inputs - write concurrent data into that row.
"11" "xxxxxxxxxxx" 0 Set First row address (DMD Row 0) and write concurrent data into that row
"11" "xxxxxxxxxxx" 1 Set Last row address (DMD last row ) - write concurrent data into that row
(Last row = 767 for DP7000, 799 for DLP650LNIR, 1079 for DLP9500)
"xxxxxxxxxxx" and "x" are don't care situations.
It is recommended NS_FLIP remain constant throughout the loading of the DMD and not change on a row cycle basis.