ZHCSA85F August 2012 – February 2019 DLPC410
The DVALID signal is a differential input signal, one for each input data bus (A/B/C/D), which indicates that data being presented to the DLPC410 is valid. DVALID assertion latches the following types of data into the DLPC410 for decoding or passing information to the DMD:
DVALID and all other inputs listed above should be synchronous to DCLKIN. DVALID can be asserted in one of the three following ways:
If the DVALID frames individual blocks or the entire DMD, ensure that block and row controls are adjusted at the proper locations in the data stream. See section DLPC410 Initialization and Training for further information.
After an active DVALID signal transitions inactive (low), DVALID should only transition to active again on even number of clocks later, i.e. 2, 4, 6, etc.