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Analog-Digital-Wandler (ADCs)
Highspeed-ADCs (≥ 10 MSPS)

ADC16DX370

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Zweikanaliger Analog-zu-Digital-Wandler (ADC), 16 Bit, 370 MSPS

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ADC3669 AKTIV 500-MSPS-ADC, 16 Bit, 2 Kanäle, mit LVDS-Schnittstelle und bis zu 32768x Dezimation Lower power, higher SNR, LVDS interface

ADC16DX370

AKTIV
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Produktdetails

Sample rate (max) (Msps) 370 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 800 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.7 Power consumption (typ) (mW) 1607 Architecture Pipeline SNR (dB) 70 ENOB (Bits) 11.2 SFDR (dB) 88 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 370 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 800 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.7 Power consumption (typ) (mW) 1607 Architecture Pipeline SNR (dB) 70 ENOB (Bits) 11.2 SFDR (dB) 88 Operating temperature range (°C) -40 to 85 Input buffer Yes
WQFN (RME) 56 64 mm² 8 x 8
  • Resolution: 16-Bit
  • Conversion Rate: 370 MSPS
  • 1.7 VP-P Input Full Scale Range
  • Performance:
    • Input: 150 MHz, –3 dBFS
      • SNR: 69.6 dBFS
      • Noise Spectral Density: –152.3 dBFS/Hz
      • SFDR: 88 dBFS
      • Non-HD2 and Non-HD3 SPUR: –90 dBFS
  • Power Dissipation: 800 mW/channel
  • Buffered Analog Inputs
  • On-Chip Precision Reference Without External Bypassing
  • Input Sampling Clock Divider With Phase Synchronization
    (Divide-by- 1, 2, 4, or 8)
  • JESD204B Subclass 1 Serial Data Interface
    • Lane Rates up to 7.4 Gb/s
    • Configurable as 1- or 2-Lanes/Channel
  • Fast Over-Range Signals
  • 4-Wire, 1.2-V, 1.8-V, 2.5-V, or 3-V Compatible Serial
    Peripheral Interface (SPI)
  • 56-Pin WQFN Package, (8 × 8 mm, 0.5-mm Pin-Pitch)
  • Resolution: 16-Bit
  • Conversion Rate: 370 MSPS
  • 1.7 VP-P Input Full Scale Range
  • Performance:
    • Input: 150 MHz, –3 dBFS
      • SNR: 69.6 dBFS
      • Noise Spectral Density: –152.3 dBFS/Hz
      • SFDR: 88 dBFS
      • Non-HD2 and Non-HD3 SPUR: –90 dBFS
  • Power Dissipation: 800 mW/channel
  • Buffered Analog Inputs
  • On-Chip Precision Reference Without External Bypassing
  • Input Sampling Clock Divider With Phase Synchronization
    (Divide-by- 1, 2, 4, or 8)
  • JESD204B Subclass 1 Serial Data Interface
    • Lane Rates up to 7.4 Gb/s
    • Configurable as 1- or 2-Lanes/Channel
  • Fast Over-Range Signals
  • 4-Wire, 1.2-V, 1.8-V, 2.5-V, or 3-V Compatible Serial
    Peripheral Interface (SPI)
  • 56-Pin WQFN Package, (8 × 8 mm, 0.5-mm Pin-Pitch)

The ADC16DX370 device is a monolithic dual-channel high performance analog-to-digital converter capable of converting analog input signals into 16-bit digital words with a sampling rate of 370 MSPS. This converter uses a differential pipelined architecture with integrated input buffer to provide excellent dynamic performance while maintaining low power consumption.

The integrated input buffer eliminates charge kickback noise coming from the internal switched capacitor sampling circuits and eases the system-level design of the driving amplifier, anti-aliasing filter, and impedance matching. An input sampling clock divider provides integer divide ratios with configurable phase selection to simplify system clocking. An integrated low-noise voltage reference eases board level design without requiring external decoupling capacitors. The output digital data is provided through a JESD204B subclass 1 interface from a 56-pin, 8-mm × 8-mm WQFN package. A SPI is available to configure the device that is compatible with 1.2-V to 3-V logic.

The ADC16DX370 device is a monolithic dual-channel high performance analog-to-digital converter capable of converting analog input signals into 16-bit digital words with a sampling rate of 370 MSPS. This converter uses a differential pipelined architecture with integrated input buffer to provide excellent dynamic performance while maintaining low power consumption.

The integrated input buffer eliminates charge kickback noise coming from the internal switched capacitor sampling circuits and eases the system-level design of the driving amplifier, anti-aliasing filter, and impedance matching. An input sampling clock divider provides integer divide ratios with configurable phase selection to simplify system clocking. An integrated low-noise voltage reference eases board level design without requiring external decoupling capacitors. The output digital data is provided through a JESD204B subclass 1 interface from a 56-pin, 8-mm × 8-mm WQFN package. A SPI is available to configure the device that is compatible with 1.2-V to 3-V logic.
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet ADC16DX370 Dual 16-Bit 370 MSPS ADC With 7.4 Gb/s JESD204B Outputs datasheet (Rev. C) PDF | HTML 20 Aug 2014
Technical article How to minimize filter loss when you drive an ADC PDF | HTML 20 Okt 2016
Technical article How to select a power-efficient narrowband receiver for active antenna-array syste PDF | HTML 12 Apr 2016
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) 19 Mär 2015
Application note Equalization Optimization of the ADC16DX370 JESD204B Serial Link 09 Sep 2014

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

ADC16DX370EVM — ADC16DX370-Evaluierungsmodul

The ADC16DX370EVM is an evaluation module used for evaluation of the ADC16DX370.  The ADC16DX370 is a low power, 16-bit, 370-MSPS analog to digital converter (ADC) with a buffered analog input, and outputs featuring a JESD204B interface operating at up to 7.4Gb/s. The EVM has (...)

Benutzerhandbuch: PDF
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Firmware

TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

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GUI für Evaluierungsmodul (EVM)

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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Simulationsmodell

ADC16DX370 IBIS Model (Rev. A)

SNVM586A.ZIP (38 KB) - IBIS Model
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Simulationstool

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

PSpice® für TI ist eine Design- und Simulationsumgebung, welche Sie dabei unterstützt, die Funktionalität analoger Schaltungen zu evaluieren. Diese Design- und Simulationssuite mit vollem Funktionsumfang verwendet eine analoge Analyse-Engine von Cadence®. PSpice für TI ist kostenlos erhältlich und (...)
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Referenzdesigns

TIDA-00360 — 700–2.700 MHz, Zweikanal-Empfänger mit 16-Bit-ADC und 100-MHz-IF-Bandbreite – Referenzdesign

The increasing demand on wireless networks to provide faster data links to customers has driven transceiver hardware to increasingly demanding performance with enough bandwidth to support the largest standardized multi-carrier frequency bands (with band aggregation in some cases) and enough (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-00353 — Referenzdesign für die Entzerrungsoptimierung von seriellen JESD204B-Schnittstellen

Employing equalization techniques is an effective way of compensating for channel loss in JESD204B high speed serial interfaces for data converters. This reference design features the ADC16DX370, a dual 16-bit, 370 MSPS analog-to-digital converter (ADC) that utilizes de-emphasis equalization to (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-00153 — Referenzdesign für JESD204B-Schnittstelle mit deterministischer Verbindungslatenz unter Verwendung e

JESD204B links are the latest trend in data-converter digital interfaces. These links take advantage of high-speed serial-digital technology to offer many compelling benefits including improved channel densities. This reference design addresses one of the challenges of adopting the new interface: (...)
Design guide: PDF
Schaltplan: PDF
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
WQFN (RME) 56 Ultra Librarian
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