Produktdetails

Resolution (Bits) 16 Number of DAC channels 2 Interface type Parallel CMOS Sample/update rate (Msps) 500 Features High Performance Rating Catalog Interpolation 1x, 2x, 4x, 8x Power consumption (typ) (mW) 1410 SFDR (dB) 78 Architecture Current Sink Operating temperature range (°C) -40 to 85 Reference type Int
Resolution (Bits) 16 Number of DAC channels 2 Interface type Parallel CMOS Sample/update rate (Msps) 500 Features High Performance Rating Catalog Interpolation 1x, 2x, 4x, 8x Power consumption (typ) (mW) 1410 SFDR (dB) 78 Architecture Current Sink Operating temperature range (°C) -40 to 85 Reference type Int
HTQFP (PZP) 100 256 mm² 16 x 16
  • 500 MSPS
  • Selectable 2×-8× Interpolation
  • On-Chip PLL/VCO Clock Multiplier
  • Full IQ Compensation Including Offset, Gain, and Phase
  • Flexible Input Options:
    • FIFO With Latch on External or Internal Clock
    • Even/Odd Multiplexed Input
    • Single Port Demultiplexed Input
  • Complex Mixer With 32-Bit NCO
  • Fixed Frequency Mixer With fS/4 and fS/2
  • 1.8-V or 3.3-V I/O Voltage
  • On-Chip 1.2-V Reference
  • Differential Scalable Output: 2 mA to 20 mA
  • Pin Compatible to DAC5686
  • High Performance
    • 81-dBc ACLR WCDMA TM1 at 30.72 MHz
    • 72-dBc ACLR WCDMA TM1 at 153.6 MHz
  • Package: 100-Pin HTQFP
  • APPLICATIONS
    • Cellular Base Transceiver Station Transmit Channel
      • CDMA: W-CDMA, CDMA2000, TD-SCDMA
      • TDMA: GSM, IS-136, EDGE/UWC-136
      • OFDM: 802.16
    • Cable Modem Termination System

PowerPAD is a trademark of Texas Instruments.
Excel is a trademark of Microsoft Corporation.
Matlab is a trademark of The MathWorks, Inc.
All other trademarks are the property of their respective owners.

  • 500 MSPS
  • Selectable 2×-8× Interpolation
  • On-Chip PLL/VCO Clock Multiplier
  • Full IQ Compensation Including Offset, Gain, and Phase
  • Flexible Input Options:
    • FIFO With Latch on External or Internal Clock
    • Even/Odd Multiplexed Input
    • Single Port Demultiplexed Input
  • Complex Mixer With 32-Bit NCO
  • Fixed Frequency Mixer With fS/4 and fS/2
  • 1.8-V or 3.3-V I/O Voltage
  • On-Chip 1.2-V Reference
  • Differential Scalable Output: 2 mA to 20 mA
  • Pin Compatible to DAC5686
  • High Performance
    • 81-dBc ACLR WCDMA TM1 at 30.72 MHz
    • 72-dBc ACLR WCDMA TM1 at 153.6 MHz
  • Package: 100-Pin HTQFP
  • APPLICATIONS
    • Cellular Base Transceiver Station Transmit Channel
      • CDMA: W-CDMA, CDMA2000, TD-SCDMA
      • TDMA: GSM, IS-136, EDGE/UWC-136
      • OFDM: 802.16
    • Cable Modem Termination System

PowerPAD is a trademark of Texas Instruments.
Excel is a trademark of Microsoft Corporation.
Matlab is a trademark of The MathWorks, Inc.
All other trademarks are the property of their respective owners.

The DAC5687 is a dual-channel 16-bit high-speed digital-to-analog converter (DAC) with integrated 2×, 4×, and 8× interpolation filters, a complex numerically controlled oscillator (NCO), onboard clock multiplier, IQ compensation, and on-chip voltage reference. The DAC5687 is pin-compatible to the DAC5686, requiring only changes in register settings for most applications, and offers additional features and superior linearity, noise, crosstalk, and PLL phase noise performance.

The DAC5687 has six signal processing blocks: two interpolate-by-two digital filters, a fine frequency mixer with 32-bit NCO, a quadrature modulation compensation block, another interpolate-by-two digital filter, and a coarse frequency mixer with fS/2 or fS/4. The different modes of operation enable or bypass the signal processing blocks.

The coarse and fine mixers can be combined to span a wider range of frequencies with fine resolution. The DAC5687 allows both complex or real output. Combining the frequency upconversion and complex output produces a Hilbert transform pair that is output from the two DACs. An external RF quadrature modulator then performs the final single-sideband upconversion.

The IQ compensation feature allows optimization of phase, gain, and offset to maximize sideband rejection and minimize LO feedthrough for an analog quadrature modulator.

The DAC5687 includes several input options: single-port interleaved data, even and odd multiplexing at half-rate, and an input FIFO with either external or internal clock to ease the input timing ambiguity when the DAC5687 is clocked at the DAC output sample rate.

The DAC5687 is a dual-channel 16-bit high-speed digital-to-analog converter (DAC) with integrated 2×, 4×, and 8× interpolation filters, a complex numerically controlled oscillator (NCO), onboard clock multiplier, IQ compensation, and on-chip voltage reference. The DAC5687 is pin-compatible to the DAC5686, requiring only changes in register settings for most applications, and offers additional features and superior linearity, noise, crosstalk, and PLL phase noise performance.

The DAC5687 has six signal processing blocks: two interpolate-by-two digital filters, a fine frequency mixer with 32-bit NCO, a quadrature modulation compensation block, another interpolate-by-two digital filter, and a coarse frequency mixer with fS/2 or fS/4. The different modes of operation enable or bypass the signal processing blocks.

The coarse and fine mixers can be combined to span a wider range of frequencies with fine resolution. The DAC5687 allows both complex or real output. Combining the frequency upconversion and complex output produces a Hilbert transform pair that is output from the two DACs. An external RF quadrature modulator then performs the final single-sideband upconversion.

The IQ compensation feature allows optimization of phase, gain, and offset to maximize sideband rejection and minimize LO feedthrough for an analog quadrature modulator.

The DAC5687 includes several input options: single-port interleaved data, even and odd multiplexing at half-rate, and an input FIFO with either external or internal clock to ease the input timing ambiguity when the DAC5687 is clocked at the DAC output sample rate.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet 16-Bit 500 MSPS 2x-8x Interpolating Dual-Channel DAC datasheet (Rev. E) 20 Sep 2006
Analog Design Journal Q3 2009 Issue Analog Applications Journal 24 Sep 2018
Application note High Speed, Digital-to-Analog Converters Basics (Rev. A) 23 Okt 2012
Analog Design Journal Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs 14 Jul 2009
Application note Passive Terminations for Current Output DACs 10 Nov 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
User guide TSW3003 Demonstration Kit (Rev. D) 28 Aug 2007
Product overview TSW3003: RF Transmit Signal Chain Demonstration Kit Bulletin 28 Sep 2006
Product overview TSW3000: DAC5687 and TRF3701/02 16-Bit, 500 MSPS DAC Coupled with Direct IQ Modu 14 Sep 2005
Application note DAC5686/DAC5687 Clock Generation Using PLL & External Clock Modes (Rev. A) 21 Jul 2005

Design und Entwicklung

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