ADS61JB23

AKTIV

Analog-Digital-Wandler (Analog-to-Digital Converter, ADC), 12 Bit, 80 MSPS

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Datenblatt

document-pdfAcrobat 12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface datasheet (Englisch)

ADS61JB23

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Sample rate (max) (Msps)

80

Resolution (Bits)

12

Number of input channels

1

Interface type

JESD204A

Analog input BW (MHz)

480

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

440

Architecture

Pipeline

SNR (dB)

71.7

ENOB (Bits)

11.5

SFDR (dB)

80

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Sample rate (max) (Msps)

80

Resolution (Bits)

12

Number of input channels

1

Interface type

JESD204A

Analog input BW (MHz)

480

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

440

Architecture

Pipeline

SNR (dB)

71.7

ENOB (Bits)

11.5

SFDR (dB)

80

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

VQFN (RHA)

40

36 mm² (6 mm × 6 mm)

Output Interface:
- Single-Lane and Dual-Lane Interfaces
- Maximum Data Rate of 1.6 Gbps
- Meets JESD204A Specification
- CML Outputs with Current Programmable from 2 mA – 32 mA
Power Dissipation:
- 440 mW at 80 MSPS in Single Lane Mode
- Power Scales Down with Clock Rate
Input Interface: Buffered Analog Inputs
71.7 dBFS SNR at 70 MHz IF
Analog Input FSR: 2 Vpp
External and Internal (trimmed) Reference Support
1.8V Supply (Analog and digital), 3.3 V Supply for Input Buffer
Programmable Digital Gain: 0dB – 6dB
Straight Offset Binary or Twos Complement Output
Package:
- 6 mm × 6 mm QFN-40

Output Interface:
- Single-Lane and Dual-Lane Interfaces
- Maximum Data Rate of 1.6 Gbps
- Meets JESD204A Specification
- CML Outputs with Current Programmable from 2 mA – 32 mA
Power Dissipation:
- 440 mW at 80 MSPS in Single Lane Mode
- Power Scales Down with Clock Rate
Input Interface: Buffered Analog Inputs
71.7 dBFS SNR at 70 MHz IF
Analog Input FSR: 2 Vpp
External and Internal (trimmed) Reference Support
1.8V Supply (Analog and digital), 3.3 V Supply for Input Buffer
Programmable Digital Gain: 0dB – 6dB
Straight Offset Binary or Twos Complement Output
Package:
- 6 mm × 6 mm QFN-40

The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated JESD204A output interface. Available in a 6 mm × 6 mm QFN package, with both single-lane and dual-lane output modes, the ADS61JB23 offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample/hold switches and higher and more consistent input impedance.

The ADS61JB23 is specified over the industrial temperature range (–40°C to 85°C).

The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated JESD204A output interface. Available in a 6 mm × 6 mm QFN package, with both single-lane and dual-lane output modes, the ADS61JB23 offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample/hold switches and higher and more consistent input impedance.

The ADS61JB23 is specified over the industrial temperature range (–40°C to 85°C).

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Technische Dokumentation

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Top-Dokumentation	Typ	Titel	Datum
*	Datenblatt	12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface datasheet	01.12.2012
	Anwendungshinweis	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	22.05.2015
	Anwendungshinweis	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	19.07.2013

Design und Entwicklung

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Firmware

TI204C-IP — Request for JESD204 rapid design IP

Die JESD204 Rapid Design IP ist dazu entwickelt worden, FPGA-Technikern einen beschleunigten Weg zu einem funktionierenden JESD204-System zu ermöglichen. Diese IP ist derart ausgelegt worden, dass nachgelagerte digitale Verarbeitung und sonstige Anwendungslogik von den meisten leistungs- und (...)