ADS62P23

AKTIV

Zweikanaliger Analog-zu-Digital-Wandler (ADC), 12 Bit, 80 MSPS

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Datenblatt

document-pdfAcrobat Dual Channel, 12Bit, 125/105/80/65 MSPS ADC with DDR LVDS/CMOS Outputs datasheet (Rev. C) (Englisch)

Benutzerhandbücher

document-pdfAcrobat
Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) (Englisch)

ADS62P23

AKTIV

Jetzt bestellen

Produktdetails

Sample rate (max) (Msps)

80

Resolution (Bits)

12

Number of input channels

2

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

450

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

587

Architecture

Pipeline

SNR (dB)

71.6

ENOB (Bits)

11.6

SFDR (dB)

93

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

80

Resolution (Bits)

12

Number of input channels

2

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

450

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

587

Architecture

Pipeline

SNR (dB)

71.6

ENOB (Bits)

11.6

SFDR (dB)

93

Operating temperature range (°C)

-40 to 85

Input buffer

No

VQFN (RGC)

64

81 mm² (9 mm × 9 mm)

Maximum Sample Rate: 125 MSPS
12-Bit Resolution with No Missing Codes
95 dB Crosstalk
Parallel CMOS and DDR LVDS Output Options
3.5 dB Coarse Gain and Programmable Fine Gain
up to 6 dB for SNR/SFDR Trade-Off
Digital Processing Block with:
- Offset Correction
- Fine Gain Correction, in Steps of 0.05 dB
- Decimation by 2/4/8
- Built-in and Custom Programmable
  24-Tap Low-/High-/Band-Pass Filters
Supports Sine, LVPECL, LVDS, and LVCMOS Clocks and
Amplitude Down to 400 mV_PP
Clock Duty Cycle Stabilizer
Internal Reference; Supports External Reference also
64-QFN Package (9mm × 9mm)
Pin Compatible 14-Bit Family (ADS62P4X)

Maximum Sample Rate: 125 MSPS
12-Bit Resolution with No Missing Codes
95 dB Crosstalk
Parallel CMOS and DDR LVDS Output Options
3.5 dB Coarse Gain and Programmable Fine Gain
up to 6 dB for SNR/SFDR Trade-Off
Digital Processing Block with:
- Offset Correction
- Fine Gain Correction, in Steps of 0.05 dB
- Decimation by 2/4/8
- Built-in and Custom Programmable
  24-Tap Low-/High-/Band-Pass Filters
Supports Sine, LVPECL, LVDS, and LVCMOS Clocks and
Amplitude Down to 400 mV_PP
Clock Duty Cycle Stabilizer
Internal Reference; Supports External Reference also
64-QFN Package (9mm × 9mm)
Pin Compatible 14-Bit Family (ADS62P4X)

ADS62P2X is a dual channel 12-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P2X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P2X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

ADS62P2X is a dual channel 12-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P2X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P2X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

filter

Andere Highspeed-ADCs (≥ 10 MSPS) suchen

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Technische Dokumentation

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Top-Dokumentation	Typ	Titel
*	Datenblatt	Dual Channel, 12Bit, 125/105/80/65 MSPS ADC with DDR LVDS/CMOS Outputs datasheet (Rev. C)	11.05.2011
*	Benutzerhandbuch	Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide)	10.07.2012
	Anwendungshinweis	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	22.05.2015
	Anwendungshinweis	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	19.07.2013
	Benutzerhandbuch	TSW4200 Demonstration Kit User's Guide (Rev. C)	31.10.2012
	Anwendungshinweis	Band-Pass Filter Design Techniques for High-Speed ADCs	27.02.2012
	Anwendungshinweis	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	10.09.2010
	Anwendungshinweis	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	28.04.2009
	Benutzerhandbuch	ADS62PxxEVM Quick Start Guide (Rev C Board) (Rev. A)	02.04.2009
	Anwendungshinweis	CDCE62005 as Clock Solution for High-Speed ADCs	04.09.2008
	Anwendungshinweis	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	08.06.2008
	Anwendungshinweis	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	02.06.2008
	Anwendungshinweis	QFN Layout Guidelines	28.07.2006

Design und Entwicklung

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