The ADS54J64 device is a quad-channel, 14-bit,
1-GSPS, analog-to-digital converter (ADC) offering wide-bandwidth, 2x oversampling and high SNR. The ADS54J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS54J64 also supports a 14-bit, 500-MSPS output in DDC bypass mode.
A four-lane JESD204B interface simplifies connectivity, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.
| Top-Dokumentation | Typ | Titel | Format-Optionen | Datum |
|---|---|---|---|---|
| * | Data sheet | ADS54J64 Quad-Channel, 14-Bit, 1-GSPS, 2x Oversampling, Analog-to-Digital Converter datasheet | PDF | HTML | 09 Okt 2017 |
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Das Evaluierungsmodul (EVM) ADS54J64 dient zur Evaluierung des ADS54J64, eines 14-Bit-Analog-zu-Digital-Wandlers (ADC) mit vier Kanälen, 1 GSPS und 2x Oversampling. Das EVM verfügt über transformatorgekoppelte Analogeingänge zum Aufnehmen eines breiten Spektrums von Signalquellen und -frequenzen. (...)
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This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
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| Gehäuse | Pins | CAD-Symbole, Footprints und 3D-Modelle |
|---|---|---|
| VQFNP (RMP) | 72 | Ultra Librarian |
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Analog Engineer's Calc Installer
General calculator tool for analog design support.
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