ADS62C17

AKTIV

Zweikanaliger Analog-zu-Digital-Wandler (ADC), 11 Bit, 200 MSPS

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Datenblatt

document-pdfAcrobat Dual Channel 11 Bit, 200 MSPS ADC with SNRBoost datasheet (Rev. A) (Englisch)

ADS62C17

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Sample rate (max) (Msps)

200

Resolution (Bits)

11

Number of input channels

2

Interface type

Parallel LVDS

Analog input BW (MHz)

700

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

1081

Architecture

Pipeline

SNR (dB)

67

ENOB (Bits)

10.8

SFDR (dB)

85

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

200

Resolution (Bits)

11

Number of input channels

2

Interface type

Parallel LVDS

Analog input BW (MHz)

700

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

1081

Architecture

Pipeline

SNR (dB)

67

ENOB (Bits)

10.8

SFDR (dB)

85

Operating temperature range (°C)

-40 to 85

Input buffer

No

VQFN (RGC)

64

81 mm² (9 mm × 9 mm)

Maximum Sample Rate: 200 MSPS
11-bit Resolution with No Missing Codes
90 dBc SFDR at Fin = 10 MHz
79.8 dBFS SNR at 125 MHz IF, 20 MHz BW
using TI proprietary SNRBoost technology
Total Power 1.1 W at 200 MSPS
90 dB Cross-talk
Double Data Rate (DDR) LVDS and Parallel
CMOS Output Options
Programmable Gain up to 6dB for SNR/SFDR Trade-off
DC Offset Correction
Gain Tuning Capability in Fine Steps (0.001 dB)
Allows Channel-to-channel Gain Matching
Supports Input Clock Amplitude Down to
400 mV p-p Differential
Internal and External Reference Support
64-QFN Package (9 mm × 9 mm)

Maximum Sample Rate: 200 MSPS
11-bit Resolution with No Missing Codes
90 dBc SFDR at Fin = 10 MHz
79.8 dBFS SNR at 125 MHz IF, 20 MHz BW
using TI proprietary SNRBoost technology
Total Power 1.1 W at 200 MSPS
90 dB Cross-talk
Double Data Rate (DDR) LVDS and Parallel
CMOS Output Options
Programmable Gain up to 6dB for SNR/SFDR Trade-off
DC Offset Correction
Gain Tuning Capability in Fine Steps (0.001 dB)
Allows Channel-to-channel Gain Matching
Supports Input Clock Amplitude Down to
400 mV p-p Differential
Internal and External Reference Support
64-QFN Package (9 mm × 9 mm)

ADS62C17 is a dual channel 11-bit, 200 MSPS A/D converter that combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.

ADS62C17 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation due to quantization noise for bandwidths less than Nyquist (Fs/2). It includes several useful and commonly used digital functions such as ADC offset correction, gain (0 to 6 dB in steps of 0.5 dB) and gain tuning (in fine steps of 0.001 dB).

The gain option can be used to improve SFDR performance at lower full-scale input ranges. Using the gain tuning capability, each channel’s gain can be set independently to improve channel-to-channel gain matching. The device also includes a dc offset correction loop that can be used to cancel the ADC offset.

Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference.

The device is specified over the industrial temperature range (–40°C to 85°C).

ADS62C17 is a dual channel 11-bit, 200 MSPS A/D converter that combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.

ADS62C17 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation due to quantization noise for bandwidths less than Nyquist (Fs/2). It includes several useful and commonly used digital functions such as ADC offset correction, gain (0 to 6 dB in steps of 0.5 dB) and gain tuning (in fine steps of 0.001 dB).

The gain option can be used to improve SFDR performance at lower full-scale input ranges. Using the gain tuning capability, each channel’s gain can be set independently to improve channel-to-channel gain matching. The device also includes a dc offset correction loop that can be used to cancel the ADC offset.

Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference.

The device is specified over the industrial temperature range (–40°C to 85°C).

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Technische Dokumentation

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Alle anzeigen 11

Top-Dokumentation	Typ	Titel	Datum
*	Datenblatt	Dual Channel 11 Bit, 200 MSPS ADC with SNRBoost datasheet (Rev. A)	17.07.2009
	Anwendungshinweis	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	22.05.2015
	Anwendungshinweis	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	19.07.2013
	Benutzerhandbuch	TSW4200 Demonstration Kit User's Guide (Rev. C)	31.10.2012
	Anwendungshinweis	Understanding Low-Amplitude Behavior of 11-bit ADCs	22.10.2011
	Anwendungshinweis	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	10.09.2010
	Anwendungshinweis	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	28.04.2009
	Anwendungshinweis	CDCE62005 as Clock Solution for High-Speed ADCs	04.09.2008
	Anwendungshinweis	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	08.06.2008
	Anwendungshinweis	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	02.06.2008
	Anwendungshinweis	QFN Layout Guidelines	28.07.2006

Design und Entwicklung

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