ZHCSK35C March 2019 – March 2021 TPS92682-Q1
PRODUCTION DATA
PWMDIV register sets the clock divider for the internal PWM generator block.
ADDR | REGISTER | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DEFAULT |
---|---|---|---|---|---|---|---|---|---|---|
09h | PWMDIV | RSVD | RSVD | RSVD | RSVD | RSVD | PWMDIV2:0 | 00000001 |
000: PWMCLK = CLKM ÷ 1
001: PWMCLK = CLKM ÷ 2
010: PWMCLK = CLKM ÷ 3
011: PWMCLK = CLKM ÷ 4
100: PWMCLK = CLKM ÷ 5
101: PWMCLK = CLKM ÷ 6
110: PWMCLK = CLKM ÷ 7
111: PWMCLK = CLKM ÷ 8