ZHCSKK3B December 2019 – February 2022 TPS6594-Q1
PRODUCTION DATA
User registers in page 0, except the ESM and the WDOG configuration registers described in Section 8.6.4.1, and the interrupt registers (x_INT) at address 0x5a through 0x6c in page 0, can be write protected by a dedicated lock. User must write '0x9B' to the REGISTER_LOCK register to unlock the register. Writing any value other than '0x9B' activates the lock again. To check the register lock status, user must read the REGISTER_LOCK_STATUS bit. When this bit is '0', it indicates the user registers are unlocked. When this bit is '1', the user registers are locked. During start-up sequence such as powering up for the first time, waking up from LP_STANDBY, or recovering from SAFE_RECOVERY, the user registers are unlocked automatically.
As an extra measure of protection to prevent the accidental change of the buck frequency while the buck is in operation, the BUCKn_FREQ_SEL register bits are locked by the REGISTER_LOCK register as well as the FREQ_SEL_UNLOCK bit. Users must set the FREQ_SEL_UNLOCK bit to '1' in addition to writing '0x9B' to the REGISTER_LOCK register in order to change the BUCKn_FREQ_SEL bit setting. The default setting of the FREQ_SEL_UNLOCK bit comes from the NVM register setting. User is advised against changing the buck frequency while the buck is in operation.