ZHCSKK3B December 2019 – February 2022 TPS6594-Q1
PRODUCTION DATA
Table 8-23 lists the memory-mapped registers for the TPS6594-Q1 registers. All register offset addresses not listed in Table 8-23 should be considered as reserved locations and the register contents should not be modified.
Complex bit access types are encoded to fit into small table cells. Table 8-24 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | W 1C | Write 1 to clear |
| WSelfClrF | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
DEV_REV is shown in Figure 8-65 and described in Table 8-25.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TI_DEVICE_ID | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | TI_DEVICE_ID | R/W | 0h | Refer to Technical Reference Manual / User's Guide for specific numbering. Note: This register can be programmed only by the manufacturer. (Default from NVM memory) |
NVM_CODE_1 is shown in Figure 8-66 and described in Table 8-26.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TI_NVM_ID | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | TI_NVM_ID | R/W | 0h | 0x00 - 0xF0 are reserved for TI manufactured NVM variants 0xF1 - 0xFF are reserved for special use 0xF1 = Engineering sample, blank NVM [trim and basic defaults only], customer programmable for engineering use only 0xF2 = Production unit, blank NVM [trim and basic defaults only], customer programmable in volume production 0xF3-FF = Reserved, do not use Note: This register can be programmed only by the manufacturer. (Default from NVM memory) |
NVM_CODE_2 is shown in Figure 8-67 and described in Table 8-27.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TI_NVM_REV | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | TI_NVM_REV | R/W | 0h | NVM revision of the IC Note: This register can be programmed only by the manufacturer. (Default from NVM memory) |
BUCK1_CTRL is shown in Figure 8-68 and described in Table 8-28.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK1_RV_SEL | RESERVED | BUCK1_PLDN | BUCK1_VMON_EN | BUCK1_VSEL | BUCK1_FPWM_MP | BUCK1_FPWM | BUCK1_EN |
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK1_RV_SEL | R/W | 0h | Select residual voltage checking for BUCK1 feedback pin. (Default from NVM memory) 0h = Disabled 1h = Enabled |
| 6 | RESERVED | R/W | 0h | |
| 5 | BUCK1_PLDN | R/W | 1h | Enable output pull-down resistor when BUCK1 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled |
| 4 | BUCK1_VMON_EN | R/W | 0h | Enable BUCK1 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled |
| 3 | BUCK1_VSEL | R/W | 0h | Select output voltage register for BUCK1: (Default from NVM memory) 0h = BUCK1_VOUT_1 1h = BUCK1_VOUT_2 |
| 2 | BUCK1_FPWM_MP | R/W | 0h | Forces the BUCK1 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. |
| 1 | BUCK1_FPWM | R/W | 1h | Forces the BUCK1 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. |
| 0 | BUCK1_EN | R/W | 0h | Enable BUCK1 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled |
BUCK1_CONF is shown in Figure 8-69 and described in Table 8-29.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK1_ILIM | BUCK1_SLEW_RATE | |||||
| R/W-0h | R/W-4h | R/W-2h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-3 | BUCK1_ILIM | R/W | 4h | Sets the switch peak current limit of BUCK1. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved |
| 2-0 | BUCK1_SLEW_RATE | R/W | 2h | Sets the output voltage slew rate for BUCK1 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs |
BUCK2_CTRL is shown in Figure 8-70 and described in Table 8-30.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK2_RV_SEL | RESERVED | BUCK2_PLDN | BUCK2_VMON_EN | BUCK2_VSEL | RESERVED | BUCK2_FPWM | BUCK2_EN |
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK2_RV_SEL | R/W | 0h | Select residual voltage checking for BUCK2 feedback pin. (Default from NVM memory) 0h = Disabled 1h = Enabled |
| 6 | RESERVED | R/W | 0h | |
| 5 | BUCK2_PLDN | R/W | 1h | Enable output pull-down resistor when BUCK2 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled |
| 4 | BUCK2_VMON_EN | R/W | 0h | Enable BUCK2 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled |
| 3 | BUCK2_VSEL | R/W | 0h | Select output voltage register for BUCK2: (Default from NVM memory) 0h = BUCK2_VOUT_1 1h = BUCK2_VOUT_2 |
| 2 | RESERVED | R/W | 0h | |
| 1 | BUCK2_FPWM | R/W | 1h | Forces the BUCK2 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. |
| 0 | BUCK2_EN | R/W | 0h | Enable BUCK2 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled |
BUCK2_CONF is shown in Figure 8-71 and described in Table 8-31.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK2_ILIM | BUCK2_SLEW_RATE | |||||
| R/W-0h | R/W-4h | R/W-2h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-3 | BUCK2_ILIM | R/W | 4h | Sets the switch peak current limit of BUCK2. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved |
| 2-0 | BUCK2_SLEW_RATE | R/W | 2h | Sets the output voltage slew rate for BUCK2 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs |
BUCK3_CTRL is shown in Figure 8-72 and described in Table 8-32.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK3_RV_SEL | RESERVED | BUCK3_PLDN | BUCK3_VMON_EN | BUCK3_VSEL | BUCK3_FPWM_MP | BUCK3_FPWM | BUCK3_EN |
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK3_RV_SEL | R/W | 0h | Select residual voltage checking for BUCK3 feedback pin. (Default from NVM memory) 0h = Disabled 1h = Enabled |
| 6 | RESERVED | R/W | 0h | |
| 5 | BUCK3_PLDN | R/W | 1h | Enable output pull-down resistor when BUCK3 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled |
| 4 | BUCK3_VMON_EN | R/W | 0h | Enable BUCK3 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled |
| 3 | BUCK3_VSEL | R/W | 0h | Select output voltage register for BUCK3: (Default from NVM memory) 0h = BUCK3_VOUT_1 1h = BUCK3_VOUT_2 |
| 2 | BUCK3_FPWM_MP | R/W | 0h | Forces the BUCK3 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. |
| 1 | BUCK3_FPWM | R/W | 1h | Forces the BUCK3 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. |
| 0 | BUCK3_EN | R/W | 0h | Enable BUCK3 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled |
BUCK3_CONF is shown in Figure 8-73 and described in Table 8-33.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK3_ILIM | BUCK3_SLEW_RATE | |||||
| R/W-0h | R/W-4h | R/W-2h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-3 | BUCK3_ILIM | R/W | 4h | Sets the switch peak current limit of BUCK3. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved |
| 2-0 | BUCK3_SLEW_RATE | R/W | 2h | Sets the output voltage slew rate for BUCK3 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs |
BUCK4_CTRL is shown in Figure 8-74 and described in Table 8-34.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_RV_SEL | RESERVED | BUCK4_PLDN | BUCK4_VMON_EN | BUCK4_VSEL | RESERVED | BUCK4_FPWM | BUCK4_EN |
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK4_RV_SEL | R/W | 0h | Select residual voltage checking for BUCK4 feedback pin. (Default from NVM memory) 0h = Disabled 1h = Enabled |
| 6 | RESERVED | R/W | 0h | |
| 5 | BUCK4_PLDN | R/W | 1h | Enable output pull-down resistor when BUCK4 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled |
| 4 | BUCK4_VMON_EN | R/W | 0h | Enable BUCK4 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled |
| 3 | BUCK4_VSEL | R/W | 0h | Select output voltage register for BUCK4: (Default from NVM memory) 0h = BUCK4_VOUT_1 1h = BUCK4_VOUT_2 |
| 2 | RESERVED | R/W | 0h | |
| 1 | BUCK4_FPWM | R/W | 1h | Forces the BUCK4 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. |
| 0 | BUCK4_EN | R/W | 0h | Enable BUCK4 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled |
BUCK4_CONF is shown in Figure 8-75 and described in Table 8-35.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK4_ILIM | BUCK4_SLEW_RATE | |||||
| R/W-0h | R/W-4h | R/W-2h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-3 | BUCK4_ILIM | R/W | 4h | Sets the switch peak current limit of BUCK4. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved |
| 2-0 | BUCK4_SLEW_RATE | R/W | 2h | Sets the output voltage slew rate for BUCK4 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs |
BUCK5_CTRL is shown in Figure 8-76 and described in Table 8-36.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK5_RV_SEL | RESERVED | BUCK5_PLDN | BUCK5_VMON_EN | BUCK5_VSEL | RESERVED | BUCK5_FPWM | BUCK5_EN |
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK5_RV_SEL | R/W | 0h | Select residual voltage checking for BUCK5 feedback pin. (Default from NVM memory) 0h = Disabled 1h = Enabled |
| 6 | RESERVED | R/W | 0h | |
| 5 | BUCK5_PLDN | R/W | 1h | Enable output pull-down resistor when BUCK5 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled |
| 4 | BUCK5_VMON_EN | R/W | 0h | Enable BUCK5 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled |
| 3 | BUCK5_VSEL | R/W | 0h | Select output voltage register for BUCK5: (Default from NVM memory) 0h = BUCK5_VOUT_1 1h = BUCK5_VOUT_2 |
| 2 | RESERVED | R/W | 0h | |
| 1 | BUCK5_FPWM | R/W | 1h | Forces the BUCK5 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. |
| 0 | BUCK5_EN | R/W | 0h | Enable BUCK5 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled |
BUCK5_CONF is shown in Figure 8-77 and described in Table 8-37.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK5_ILIM | BUCK5_SLEW_RATE | |||||
| R/W-0h | R/W-4h | R/W-2h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-3 | BUCK5_ILIM | R/W | 4h | Sets the switch peak current limit of BUCK5. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = Reserved 5h = Reserved 6h = Reserved 7h = Reserved |
| 2-0 | BUCK5_SLEW_RATE | R/W | 2h | Sets the output voltage slew rate for BUCK5 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs |
BUCK1_VOUT_1 is shown in Figure 8-78 and described in Table 8-38.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK1_VSET1 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | BUCK1_VSET1 | R/W | 0h | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK1_VOUT_2 is shown in Figure 8-79 and described in Table 8-39.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK1_VSET2 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | BUCK1_VSET2 | R/W | 0h | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK2_VOUT_1 is shown in Figure 8-80 and described in Table 8-40.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK2_VSET1 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | BUCK2_VSET1 | R/W | 0h | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK2_VOUT_2 is shown in Figure 8-81 and described in Table 8-41.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK2_VSET2 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | BUCK2_VSET2 | R/W | 0h | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK3_VOUT_1 is shown in Figure 8-82 and described in Table 8-42.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK3_VSET1 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | BUCK3_VSET1 | R/W | 0h | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK3_VOUT_2 is shown in Figure 8-83 and described in Table 8-43.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK3_VSET2 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | BUCK3_VSET2 | R/W | 0h | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK4_VOUT_1 is shown in Figure 8-84 and described in Table 8-44.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_VSET1 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | BUCK4_VSET1 | R/W | 0h | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK4_VOUT_2 is shown in Figure 8-85 and described in Table 8-45.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_VSET2 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | BUCK4_VSET2 | R/W | 0h | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK5_VOUT_1 is shown in Figure 8-86 and described in Table 8-46.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK5_VSET1 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | BUCK5_VSET1 | R/W | 0h | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK5_VOUT_2 is shown in Figure 8-87 and described in Table 8-47.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK5_VSET2 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | BUCK5_VSET2 | R/W | 0h | Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) |
BUCK1_PG_WINDOW is shown in Figure 8-88 and described in Table 8-48.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK1_UV_THR | BUCK1_OV_THR | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-3 | BUCK1_UV_THR | R/W | 0h | Powergood low threshold level for BUCK1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV |
| 2-0 | BUCK1_OV_THR | R/W | 0h | Powergood high threshold level for BUCK1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV |
BUCK2_PG_WINDOW is shown in Figure 8-89 and described in Table 8-49.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK2_UV_THR | BUCK2_OV_THR | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-3 | BUCK2_UV_THR | R/W | 0h | Powergood low threshold level for BUCK2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV |
| 2-0 | BUCK2_OV_THR | R/W | 0h | Powergood high threshold level for BUCK2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV |
BUCK3_PG_WINDOW is shown in Figure 8-90 and described in Table 8-50.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK3_UV_THR | BUCK3_OV_THR | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-3 | BUCK3_UV_THR | R/W | 0h | Powergood low threshold level for BUCK3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV |
| 2-0 | BUCK3_OV_THR | R/W | 0h | Powergood high threshold level for BUCK3: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV |
BUCK4_PG_WINDOW is shown in Figure 8-91 and described in Table 8-51.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK4_UV_THR | BUCK4_OV_THR | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-3 | BUCK4_UV_THR | R/W | 0h | Powergood low threshold level for BUCK4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV |
| 2-0 | BUCK4_OV_THR | R/W | 0h | Powergood high threshold level for BUCK4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV |
BUCK5_PG_WINDOW is shown in Figure 8-92 and described in Table 8-52.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK5_UV_THR | BUCK5_OV_THR | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-3 | BUCK5_UV_THR | R/W | 0h | Powergood low threshold level for BUCK5: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV |
| 2-0 | BUCK5_OV_THR | R/W | 0h | Powergood high threshold level for BUCK5: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV |
LDO1_CTRL is shown in Figure 8-93 and described in Table 8-53.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO1_RV_SEL | LDO1_PLDN | LDO1_VMON_EN | RESERVED | LDO1_SLOW_RAMP | LDO1_EN | ||
| R/W-0h | R/W-3h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LDO1_RV_SEL | R/W | 0h | Select residual voltage checking for LDO1 output pin. (Default from NVM memory) 0h = Disabled 1h = Enabled |
| 6-5 | LDO1_PLDN | R/W | 3h | Enable output pull-down resistor when LDO1 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm |
| 4 | LDO1_VMON_EN | R/W | 0h | Enable LDO1 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. |
| 3-2 | RESERVED | R/W | 0h | |
| 1 | LDO1_SLOW_RAMP | R/W | 0h | LDO1 start-up slew rate selection
0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET |
| 0 | LDO1_EN | R/W | 0h | Enable LDO1 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. |
LDO2_CTRL is shown in Figure 8-94 and described in Table 8-54.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO2_RV_SEL | LDO2_PLDN | LDO2_VMON_EN | RESERVED | LDO2_SLOW_RAMP | LDO2_EN | ||
| R/W-0h | R/W-3h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LDO2_RV_SEL | R/W | 0h | Select residual voltage checking for LDO2 output pin. (Default from NVM memory) 0h = Disabled 1h = Enabled |
| 6-5 | LDO2_PLDN | R/W | 3h | Enable output pull-down resistor when LDO2 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm |
| 4 | LDO2_VMON_EN | R/W | 0h | Enable LDO2 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. |
| 3-2 | RESERVED | R/W | 0h | |
| 1 | LDO2_SLOW_RAMP | R/W | 0h | LDO2 start-up slew rate selection
0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET |
| 0 | LDO2_EN | R/W | 0h | Enable LDO2 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. |
LDO3_CTRL is shown in Figure 8-95 and described in Table 8-55.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO3_RV_SEL | LDO3_PLDN | LDO3_VMON_EN | RESERVED | LDO3_SLOW_RAMP | LDO3_EN | ||
| R/W-0h | R/W-3h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LDO3_RV_SEL | R/W | 0h | Select residual voltage checking for LDO3 output pin. (Default from NVM memory) 0h = Disabled 1h = Enabled |
| 6-5 | LDO3_PLDN | R/W | 3h | Enable output pull-down resistor when LDO3 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm |
| 4 | LDO3_VMON_EN | R/W | 0h | Enable LDO3 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. |
| 3-2 | RESERVED | R/W | 0h | |
| 1 | LDO3_SLOW_RAMP | R/W | 0h | LDO3 start-up slew rate selection
0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET |
| 0 | LDO3_EN | R/W | 0h | Enable LDO3 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. |
LDO4_CTRL is shown in Figure 8-96 and described in Table 8-56.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO4_RV_SEL | LDO4_PLDN | LDO4_VMON_EN | RESERVED | LDO4_SLOW_RAMP | LDO4_EN | ||
| R/W-0h | R/W-3h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LDO4_RV_SEL | R/W | 0h | Select residual voltage checking for LDO4 output pin. (Default from NVM memory) 0h = Disabled 1h = Enabled |
| 6-5 | LDO4_PLDN | R/W | 3h | Enable output pull-down resistor when LDO4 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm |
| 4 | LDO4_VMON_EN | R/W | 0h | Enable LDO4 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. |
| 3-2 | RESERVED | R/W | 0h | |
| 1 | LDO4_SLOW_RAMP | R/W | 0h | LDO4 start-up slew rate selection
0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET |
| 0 | LDO4_EN | R/W | 0h | Enable LDO4 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. |
LDORTC_CTRL is shown in Figure 8-97 and described in Table 8-57.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LDORTC_DIS | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-1 | RESERVED | R/W | 0h | |
| 0 | LDORTC_DIS | R/W | 0h | Disable LDORTC regulator:
0h = LDORTC regulator is enabled 1h = LDORTC regulator is disabled |
LDO1_VOUT is shown in Figure 8-98 and described in Table 8-58.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO1_BYPASS | LDO1_VSET | RESERVED | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LDO1_BYPASS | R/W | 0h | Set LDO1 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. |
| 6-1 | LDO1_VSET | R/W | 0h | Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) |
| 0 | RESERVED | R/W | 0h |
LDO2_VOUT is shown in Figure 8-99 and described in Table 8-59.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO2_BYPASS | LDO2_VSET | RESERVED | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LDO2_BYPASS | R/W | 0h | Set LDO2 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. |
| 6-1 | LDO2_VSET | R/W | 0h | Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) |
| 0 | RESERVED | R/W | 0h |
LDO3_VOUT is shown in Figure 8-100 and described in Table 8-60.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO3_BYPASS | LDO3_VSET | RESERVED | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LDO3_BYPASS | R/W | 0h | Set LDO3 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. |
| 6-1 | LDO3_VSET | R/W | 0h | Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) |
| 0 | RESERVED | R/W | 0h |
LDO4_VOUT is shown in Figure 8-101 and described in Table 8-61.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LDO4_VSET | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0h | |
| 6-0 | LDO4_VSET | R/W | 0h | Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) |
LDO1_PG_WINDOW is shown in Figure 8-102 and described in Table 8-62.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LDO1_UV_THR | LDO1_OV_THR | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-3 | LDO1_UV_THR | R/W | 0h | Powergood low threshold level for LDO1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV |
| 2-0 | LDO1_OV_THR | R/W | 0h | Powergood high threshold level for LDO1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV |
LDO2_PG_WINDOW is shown in Figure 8-103 and described in Table 8-63.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LDO2_UV_THR | LDO2_OV_THR | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-3 | LDO2_UV_THR | R/W | 0h | Powergood low threshold level for LDO2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV |
| 2-0 | LDO2_OV_THR | R/W | 0h | Powergood high threshold level for LDO2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV |
LDO3_PG_WINDOW is shown in Figure 8-104 and described in Table 8-64.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LDO3_UV_THR | LDO3_OV_THR | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-3 | LDO3_UV_THR | R/W | 0h | Powergood low threshold level for LDO3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV |
| 2-0 | LDO3_OV_THR | R/W | 0h | Powergood high threshold level for LDO3: Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV |
LDO4_PG_WINDOW is shown in Figure 8-105 and described in Table 8-65.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LDO4_UV_THR | LDO4_OV_THR | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-3 | LDO4_UV_THR | R/W | 0h | Powergood low threshold level for LDO4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV |
| 2-0 | LDO4_OV_THR | R/W | 0h | Powergood high threshold level for LDO4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV |
VCCA_VMON_CTRL is shown in Figure 8-106 and described in Table 8-66.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VMON_DEGLITCH_SEL | RESERVED | VCCA_VMON_EN | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5 | VMON_DEGLITCH_SEL | R/W | 0h | Deglitch time select for BUCKx_VMON, LDOx_VMON and VCCA_VMON (Default from NVM memory) 0h = 4 us 1h = 20 us |
| 4-1 | RESERVED | R/W | 0h | |
| 0 | VCCA_VMON_EN | R/W | 0h | Enable VCCA OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. |
VCCA_PG_WINDOW is shown in Figure 8-107 and described in Table 8-67.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VCCA_PG_SET | VCCA_UV_THR | VCCA_OV_THR | ||||
| R/W-0h | R/W-1h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0h | |
| 6 | VCCA_PG_SET | R/W | 1h | Powergood level for VCCA pin: (Default from NVM memory) 0h = 3.3 V 1h = 5.0 V |
| 5-3 | VCCA_UV_THR | R/W | 0h | Powergood low threshold level for VCCA pin: (Default from NVM memory) 0h = -3% 1h = -3.5% 2h = -4% 3h = -5% 4h = -6% 5h = -7% 6h = -8% 7h = -10% |
| 2-0 | VCCA_OV_THR | R/W | 0h | Powergood high threshold level for VCCA pin: (Default from NVM memory) 0h = +3% 1h = +3.5% 2h = +4% 3h = +5% 4h = +6% 5h = +7% 6h = +8% 7h = +10% |
GPIO1_CONF is shown in Figure 8-108 and described in Table 8-68.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO1_SEL | GPIO1_DEGLITCH_EN | GPIO1_PU_PD_EN | GPIO1_PU_SEL | GPIO1_OD | GPIO1_DIR | ||
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | GPIO1_SEL | R/W | 0h | GPIO1 signal function: (Default from NVM memory) 0h = GPIO1 1h = SCL_I2C2/CS_SPI 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 |
| 4 | GPIO1_DEGLITCH_EN | R/W | 0h | GPIO1 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. |
| 3 | GPIO1_PU_PD_EN | R/W | 1h | Control for GPIO1 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled |
| 2 | GPIO1_PU_SEL | R/W | 0h | Control for GPIO1 pin pull-up/pull-down resistor: GPIO1_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected |
| 1 | GPIO1_OD | R/W | 1h | GPIO1 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output |
| 0 | GPIO1_DIR | R/W | 0h | GPIO1 signal direction: (Default from NVM memory) 0h = Input 1h = Output |
GPIO2_CONF is shown in Figure 8-109 and described in Table 8-69.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO2_SEL | GPIO2_DEGLITCH_EN | GPIO2_PU_PD_EN | GPIO2_PU_SEL | GPIO2_OD | GPIO2_DIR | ||
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | GPIO2_SEL | R/W | 0h | GPIO2 signal function: (Default from NVM memory) 0h = GPIO2 1h = TRIG_WDOG 2h = SDA_I2C2/SDO_SPI 3h = SDA_I2C2/SDO_SPI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 |
| 4 | GPIO2_DEGLITCH_EN | R/W | 0h | GPIO2 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. |
| 3 | GPIO2_PU_PD_EN | R/W | 1h | Control for GPIO2 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled |
| 2 | GPIO2_PU_SEL | R/W | 0h | Control for GPIO2 pin pull-up/pull-down resistor: GPIO2_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected |
| 1 | GPIO2_OD | R/W | 1h | GPIO2 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output |
| 0 | GPIO2_DIR | R/W | 0h | GPIO2 signal direction: (Default from NVM memory) 0h = Input 1h = Output |
GPIO3_CONF is shown in Figure 8-110 and described in Table 8-70.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO3_SEL | GPIO3_DEGLITCH_EN | GPIO3_PU_PD_EN | GPIO3_PU_SEL | GPIO3_OD | GPIO3_DIR | ||
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | GPIO3_SEL | R/W | 0h | GPIO3 signal function: (Default from NVM memory) 0h = GPIO3 1h = CLK32KOUT 2h = NERR_SOC 3h = NERR_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 |
| 4 | GPIO3_DEGLITCH_EN | R/W | 0h | GPIO3 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. |
| 3 | GPIO3_PU_PD_EN | R/W | 1h | Control for GPIO3 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled |
| 2 | GPIO3_PU_SEL | R/W | 0h | Control for GPIO3 pin pull-up/pull-down resistor: GPIO3_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected |
| 1 | GPIO3_OD | R/W | 1h | GPIO3 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output |
| 0 | GPIO3_DIR | R/W | 0h | GPIO3 signal direction: (Default from NVM memory) 0h = Input 1h = Output |
GPIO4_CONF is shown in Figure 8-111 and described in Table 8-71.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO4_SEL | GPIO4_DEGLITCH_EN | GPIO4_PU_PD_EN | GPIO4_PU_SEL | GPIO4_OD | GPIO4_DIR | ||
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | GPIO4_SEL | R/W | 0h | GPIO4 signal function: (Default from NVM memory) 0h = GPIO4 1h = CLK32KOUT 2h = CLK32KOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 |
| 4 | GPIO4_DEGLITCH_EN | R/W | 0h | GPIO4 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. |
| 3 | GPIO4_PU_PD_EN | R/W | 1h | Control for GPIO4 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled |
| 2 | GPIO4_PU_SEL | R/W | 0h | Control for GPIO4 pin pull-up/pull-down resistor: GPIO4_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected |
| 1 | GPIO4_OD | R/W | 1h | GPIO4 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output |
| 0 | GPIO4_DIR | R/W | 0h | GPIO4 signal direction: (Default from NVM memory) 0h = Input 1h = Output |
GPIO5_CONF is shown in Figure 8-112 and described in Table 8-72.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO5_SEL | GPIO5_DEGLITCH_EN | GPIO5_PU_PD_EN | GPIO5_PU_SEL | GPIO5_OD | GPIO5_DIR | ||
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | GPIO5_SEL | R/W | 0h | GPIO5 signal function: (Default from NVM memory) 0h = GPIO5 1h = SCLK_SPMI 2h = SCLK_SPMI 3h = SCLK_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 |
| 4 | GPIO5_DEGLITCH_EN | R/W | 0h | GPIO5 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. |
| 3 | GPIO5_PU_PD_EN | R/W | 1h | Control for GPIO5 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled |
| 2 | GPIO5_PU_SEL | R/W | 0h | Control for GPIO5 pin pull-up/pull-down resistor: GPIO5_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected |
| 1 | GPIO5_OD | R/W | 1h | GPIO5 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output |
| 0 | GPIO5_DIR | R/W | 0h | GPIO5 signal direction: (Default from NVM memory) 0h = Input 1h = Output |
GPIO6_CONF is shown in Figure 8-113 and described in Table 8-73.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO6_SEL | GPIO6_DEGLITCH_EN | GPIO6_PU_PD_EN | GPIO6_PU_SEL | GPIO6_OD | GPIO6_DIR | ||
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | GPIO6_SEL | R/W | 0h | GPIO6 signal function: (Default from NVM memory) 0h = GPIO6 1h = SDATA_SPMI 2h = SDATA_SPMI 3h = SDATA_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 |
| 4 | GPIO6_DEGLITCH_EN | R/W | 0h | GPIO6 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. |
| 3 | GPIO6_PU_PD_EN | R/W | 1h | Control for GPIO6 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled |
| 2 | GPIO6_PU_SEL | R/W | 0h | Control for GPIO6 pin pull-up/pull-down resistor: GPIO6_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected |
| 1 | GPIO6_OD | R/W | 1h | GPIO6 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output |
| 0 | GPIO6_DIR | R/W | 0h | GPIO6 signal direction: (Default from NVM memory) 0h = Input 1h = Output |
GPIO7_CONF is shown in Figure 8-114 and described in Table 8-74.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO7_SEL | GPIO7_DEGLITCH_EN | GPIO7_PU_PD_EN | GPIO7_PU_SEL | GPIO7_OD | GPIO7_DIR | ||
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | GPIO7_SEL | R/W | 0h | GPIO7 signal function: (Default from NVM memory) 0h = GPIO7 1h = NERR_MCU 2h = NERR_MCU 3h = NERR_MCU 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 |
| 4 | GPIO7_DEGLITCH_EN | R/W | 0h | GPIO7 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. |
| 3 | GPIO7_PU_PD_EN | R/W | 1h | Control for GPIO7 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled |
| 2 | GPIO7_PU_SEL | R/W | 0h | Control for GPIO7 pin pull-up/pull-down resistor: GPIO7_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected |
| 1 | GPIO7_OD | R/W | 1h | GPIO7 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output |
| 0 | GPIO7_DIR | R/W | 0h | GPIO7 signal direction: (Default from NVM memory) 0h = Input 1h = Output |
GPIO8_CONF is shown in Figure 8-115 and described in Table 8-75.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO8_SEL | GPIO8_DEGLITCH_EN | GPIO8_PU_PD_EN | GPIO8_PU_SEL | GPIO8_OD | GPIO8_DIR | ||
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | GPIO8_SEL | R/W | 0h | GPIO8 signal function: (Default from NVM memory) 0h = GPIO8 1h = CLK32KOUT 2h = SYNCCLKOUT 3h = DISABLE_WDOG 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 |
| 4 | GPIO8_DEGLITCH_EN | R/W | 0h | GPIO8 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. |
| 3 | GPIO8_PU_PD_EN | R/W | 1h | Control for GPIO8 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled |
| 2 | GPIO8_PU_SEL | R/W | 0h | Control for GPIO8 pin pull-up/pull-down resistor: GPIO8_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected |
| 1 | GPIO8_OD | R/W | 1h | GPIO8 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output |
| 0 | GPIO8_DIR | R/W | 0h | GPIO8 signal direction: (Default from NVM memory) 0h = Input 1h = Output |
GPIO9_CONF is shown in Figure 8-116 and described in Table 8-76.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO9_SEL | GPIO9_DEGLITCH_EN | GPIO9_PU_PD_EN | GPIO9_PU_SEL | GPIO9_OD | GPIO9_DIR | ||
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | GPIO9_SEL | R/W | 0h | GPIO9 signal function: (Default from NVM memory) 0h = GPIO9 1h = PGOOD 2h = DISABLE_WDOG 3h = SYNCCLKOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 |
| 4 | GPIO9_DEGLITCH_EN | R/W | 0h | GPIO9 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. |
| 3 | GPIO9_PU_PD_EN | R/W | 1h | Control for GPIO9 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled |
| 2 | GPIO9_PU_SEL | R/W | 0h | Control for GPIO9 pin pull-up/pull-down resistor: GPIO9_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected |
| 1 | GPIO9_OD | R/W | 1h | GPIO9 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output |
| 0 | GPIO9_DIR | R/W | 0h | GPIO9 signal direction: (Default from NVM memory) 0h = Input 1h = Output |
GPIO10_CONF is shown in Figure 8-117 and described in Table 8-77.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO10_SEL | GPIO10_DEGLITCH_EN | GPIO10_PU_PD_EN | GPIO10_PU_SEL | GPIO10_OD | GPIO10_DIR | ||
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | GPIO10_SEL | R/W | 0h | GPIO10 signal function: (Default from NVM memory) 0h = GPIO10 1h = SYNCCLKIN 2h = SYNCCLKOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 |
| 4 | GPIO10_DEGLITCH_EN | R/W | 0h | GPIO10 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. |
| 3 | GPIO10_PU_PD_EN | R/W | 1h | Control for GPIO10 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled |
| 2 | GPIO10_PU_SEL | R/W | 0h | Control for GPIO10 pin pull-up/pull-down resistor: GPIO10_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected |
| 1 | GPIO10_OD | R/W | 1h | GPIO10 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output |
| 0 | GPIO10_DIR | R/W | 0h | GPIO10 signal direction: (Default from NVM memory) 0h = Input 1h = Output |
GPIO11_CONF is shown in Figure 8-118 and described in Table 8-78.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO11_SEL | GPIO11_DEGLITCH_EN | GPIO11_PU_PD_EN | GPIO11_PU_SEL | GPIO11_OD | GPIO11_DIR | ||
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-1h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | GPIO11_SEL | R/W | 0h | GPIO11 signal function: (Default from NVM memory) 0h = GPIO11 1h = TRIG_WDOG 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 |
| 4 | GPIO11_DEGLITCH_EN | R/W | 0h | GPIO11 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. |
| 3 | GPIO11_PU_PD_EN | R/W | 1h | Control for GPIO11 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled |
| 2 | GPIO11_PU_SEL | R/W | 0h | Control for GPIO11 pin pull-up/pull-down resistor: GPIO11_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected |
| 1 | GPIO11_OD | R/W | 1h | GPIO11 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output |
| 0 | GPIO11_DIR | R/W | 0h | GPIO11 signal direction: (Default from NVM memory) 0h = Input 1h = Output |
NPWRON_CONF is shown in Figure 8-119 and described in Table 8-79.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NPWRON_SEL | ENABLE_POL | ENABLE_DEGLITCH_EN | ENABLE_PU_PD_EN | ENABLE_PU_SEL | RESERVED | NRSTOUT_OD | |
| R/W-2h | R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | NPWRON_SEL | R/W | 2h | NPWRON/ENABLE signal function: (Default from NVM memory) 0h = ENABLE 1h = NPWRON 2h = None 3h = None |
| 5 | ENABLE_POL | R/W | 0h | Control for ENABLE pin polarity: (Default from NVM memory) 0h = Active high 1h = Active low |
| 4 | ENABLE_DEGLITCH_EN | R/W | 0h | NPWRON/ENABLE signal deglitch time: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. |
| 3 | ENABLE_PU_PD_EN | R/W | 1h | Control for NPWRON/ENABLE pin pull-up resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled |
| 2 | ENABLE_PU_SEL | R/W | 0h | Control for NPWRON/ENABLE pin pull-down resistor: ENABLE_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected |
| 1 | RESERVED | R/W | 0h | |
| 0 | NRSTOUT_OD | R/W | 0h | NRSTOUT signal type: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output |
GPIO_OUT_1 is shown in Figure 8-120 and described in Table 8-80.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO8_OUT | GPIO7_OUT | GPIO6_OUT | GPIO5_OUT | GPIO4_OUT | GPIO3_OUT | GPIO2_OUT | GPIO1_OUT |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO8_OUT | R/W | 0h | Control for GPIO8 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High |
| 6 | GPIO7_OUT | R/W | 0h | Control for GPIO7 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High |
| 5 | GPIO6_OUT | R/W | 0h | Control for GPIO6 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High |
| 4 | GPIO5_OUT | R/W | 0h | Control for GPIO5 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High |
| 3 | GPIO4_OUT | R/W | 0h | Control for GPIO4 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High |
| 2 | GPIO3_OUT | R/W | 0h | Control for GPIO3 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High |
| 1 | GPIO2_OUT | R/W | 0h | Control for GPIO2 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High |
| 0 | GPIO1_OUT | R/W | 0h | Control for GPIO1 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High |
GPIO_OUT_2 is shown in Figure 8-121 and described in Table 8-81.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GPIO11_OUT | GPIO10_OUT | GPIO9_OUT | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-3 | RESERVED | R/W | 0h | |
| 2 | GPIO11_OUT | R/W | 0h | Control for GPIO11 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High |
| 1 | GPIO10_OUT | R/W | 0h | Control for GPIO10 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High |
| 0 | GPIO9_OUT | R/W | 0h | Control for GPIO9 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High |
GPIO_IN_1 is shown in Figure 8-122 and described in Table 8-82.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO8_IN | GPIO7_IN | GPIO6_IN | GPIO5_IN | GPIO4_IN | GPIO3_IN | GPIO2_IN | GPIO1_IN |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO8_IN | R | 0h | Level of GPIO8 signal:
0h = Low 1h = High |
| 6 | GPIO7_IN | R | 0h | Level of GPIO7 signal:
0h = Low 1h = High |
| 5 | GPIO6_IN | R | 0h | Level of GPIO6 signal:
0h = Low 1h = High |
| 4 | GPIO5_IN | R | 0h | Level of GPIO5 signal:
0h = Low 1h = High |
| 3 | GPIO4_IN | R | 0h | Level of GPIO4 signal:
0h = Low 1h = High |
| 2 | GPIO3_IN | R | 0h | Level of GPIO3 signal:
0h = Low 1h = High |
| 1 | GPIO2_IN | R | 0h | Level of GPIO2 signal:
0h = Low 1h = High |
| 0 | GPIO1_IN | R | 0h | Level of GPIO1 signal:
0h = Low 1h = High |
GPIO_IN_2 is shown in Figure 8-123 and described in Table 8-83.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NPWRON_IN | GPIO11_IN | GPIO10_IN | GPIO9_IN | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R | 0h | |
| 3 | NPWRON_IN | R | 0h | Level of NPWRON/ENABLE signal:
0h = Low 1h = High |
| 2 | GPIO11_IN | R | 0h | Level of GPIO11 signal:
0h = Low 1h = High |
| 1 | GPIO10_IN | R | 0h | Level of GPIO10 signal:
0h = Low 1h = High |
| 0 | GPIO9_IN | R | 0h | Level of GPIO9 signal:
0h = Low 1h = High |
RAIL_SEL_1 is shown in Figure 8-124 and described in Table 8-84.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_GRP_SEL | BUCK3_GRP_SEL | BUCK2_GRP_SEL | BUCK1_GRP_SEL | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | BUCK4_GRP_SEL | R/W | 0h | Rail group selection for BUCK4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group |
| 5-4 | BUCK3_GRP_SEL | R/W | 0h | Rail group selection for BUCK3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group |
| 3-2 | BUCK2_GRP_SEL | R/W | 0h | Rail group selection for BUCK2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group |
| 1-0 | BUCK1_GRP_SEL | R/W | 0h | Rail group selection for BUCK1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group |
RAIL_SEL_2 is shown in Figure 8-125 and described in Table 8-85.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO3_GRP_SEL | LDO2_GRP_SEL | LDO1_GRP_SEL | BUCK5_GRP_SEL | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | LDO3_GRP_SEL | R/W | 0h | Rail group selection for LDO3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group |
| 5-4 | LDO2_GRP_SEL | R/W | 0h | Rail group selection for LDO2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group |
| 3-2 | LDO1_GRP_SEL | R/W | 0h | Rail group selection for LDO1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group |
| 1-0 | BUCK5_GRP_SEL | R/W | 0h | Rail group selection for BUCK5: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group |
RAIL_SEL_3 is shown in Figure 8-126 and described in Table 8-86.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VCCA_GRP_SEL | LDO4_GRP_SEL | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R/W | 0h | |
| 3-2 | VCCA_GRP_SEL | R/W | 0h | Rail group selection for VCCA monitoring: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group |
| 1-0 | LDO4_GRP_SEL | R/W | 0h | Rail group selection for LDO4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group |
FSM_TRIG_SEL_1 is shown in Figure 8-127 and described in Table 8-87.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SEVERE_ERR_TRIG | OTHER_RAIL_TRIG | SOC_RAIL_TRIG | MCU_RAIL_TRIG | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | SEVERE_ERR_TRIG | R/W | 0h | Trigger selection for Severe Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error |
| 5-4 | OTHER_RAIL_TRIG | R/W | 0h | Trigger selection for OTHER rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error |
| 3-2 | SOC_RAIL_TRIG | R/W | 0h | Trigger selection for SOC rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error |
| 1-0 | MCU_RAIL_TRIG | R/W | 0h | Trigger selection for MCU rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error |
FSM_TRIG_SEL_2 is shown in Figure 8-128 and described in Table 8-88.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MODERATE_ERR_TRIG | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | RESERVED | R/W | 0h | |
| 1-0 | MODERATE_ERR_TRIG | R/W | 0h | Trigger selection for Moderate Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error |
FSM_TRIG_MASK_1 is shown in Figure 8-129 and described in Table 8-89.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO4_FSM_MASK_POL | GPIO4_FSM_MASK | GPIO3_FSM_MASK_POL | GPIO3_FSM_MASK | GPIO2_FSM_MASK_POL | GPIO2_FSM_MASK | GPIO1_FSM_MASK_POL | GPIO1_FSM_MASK |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO4_FSM_MASK_POL | R/W | 0h | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' |
| 6 | GPIO4_FSM_MASK | R/W | 0h | FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked |
| 5 | GPIO3_FSM_MASK_POL | R/W | 0h | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' |
| 4 | GPIO3_FSM_MASK | R/W | 0h | FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked |
| 3 | GPIO2_FSM_MASK_POL | R/W | 0h | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' |
| 2 | GPIO2_FSM_MASK | R/W | 0h | FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked |
| 1 | GPIO1_FSM_MASK_POL | R/W | 0h | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' |
| 0 | GPIO1_FSM_MASK | R/W | 0h | FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked |
FSM_TRIG_MASK_2 is shown in Figure 8-130 and described in Table 8-90.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO8_FSM_MASK_POL | GPIO8_FSM_MASK | GPIO7_FSM_MASK_POL | GPIO7_FSM_MASK | GPIO6_FSM_MASK_POL | GPIO6_FSM_MASK | GPIO5_FSM_MASK_POL | GPIO5_FSM_MASK |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO8_FSM_MASK_POL | R/W | 0h | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' |
| 6 | GPIO8_FSM_MASK | R/W | 0h | FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked |
| 5 | GPIO7_FSM_MASK_POL | R/W | 0h | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' |
| 4 | GPIO7_FSM_MASK | R/W | 0h | FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked |
| 3 | GPIO6_FSM_MASK_POL | R/W | 0h | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' |
| 2 | GPIO6_FSM_MASK | R/W | 0h | FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked |
| 1 | GPIO5_FSM_MASK_POL | R/W | 0h | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' |
| 0 | GPIO5_FSM_MASK | R/W | 0h | FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked |
FSM_TRIG_MASK_3 is shown in Figure 8-131 and described in Table 8-91.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GPIO11_FSM_MASK_POL | GPIO11_FSM_MASK | GPIO10_FSM_MASK_POL | GPIO10_FSM_MASK | GPIO9_FSM_MASK_POL | GPIO9_FSM_MASK | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5 | GPIO11_FSM_MASK_POL | R/W | 0h | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' |
| 4 | GPIO11_FSM_MASK | R/W | 0h | FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked |
| 3 | GPIO10_FSM_MASK_POL | R/W | 0h | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' |
| 2 | GPIO10_FSM_MASK | R/W | 0h | FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked |
| 1 | GPIO9_FSM_MASK_POL | R/W | 0h | FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' |
| 0 | GPIO9_FSM_MASK | R/W | 0h | FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked |
MASK_BUCK1_2 is shown in Figure 8-132 and described in Table 8-92.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK2_ILIM_MASK | RESERVED | BUCK2_UV_MASK | BUCK2_OV_MASK | BUCK1_ILIM_MASK | RESERVED | BUCK1_UV_MASK | BUCK1_OV_MASK |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK2_ILIM_MASK | R/W | 0h | Masking for BUCK2 current monitoring interrupt BUCK2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 6 | RESERVED | R/W | 0h | |
| 5 | BUCK2_UV_MASK | R/W | 0h | Masking of BUCK2 under-voltage detection interrupt BUCK2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 4 | BUCK2_OV_MASK | R/W | 0h | Masking of BUCK2 over-voltage detection interrupt BUCK2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 3 | BUCK1_ILIM_MASK | R/W | 0h | Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 2 | RESERVED | R/W | 0h | |
| 1 | BUCK1_UV_MASK | R/W | 0h | Masking of BUCK1 under-voltage detection interrupt BUCK1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | BUCK1_OV_MASK | R/W | 0h | Masking of BUCK1 over-voltage detection interrupt BUCK1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
MASK_BUCK3_4 is shown in Figure 8-133 and described in Table 8-93.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_ILIM_MASK | RESERVED | BUCK4_UV_MASK | BUCK4_OV_MASK | BUCK3_ILIM_MASK | RESERVED | BUCK3_UV_MASK | BUCK3_OV_MASK |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK4_ILIM_MASK | R/W | 0h | Masking for BUCK4 current monitoring interrupt BUCK4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 6 | RESERVED | R/W | 0h | |
| 5 | BUCK4_UV_MASK | R/W | 0h | Masking of BUCK4 under-voltage detection interrupt BUCK4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 4 | BUCK4_OV_MASK | R/W | 0h | Masking of BUCK4 over-voltage detection interrupt BUCK4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 3 | BUCK3_ILIM_MASK | R/W | 0h | Masking for BUCK3 current monitoring interrupt BUCK3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 2 | RESERVED | R/W | 0h | |
| 1 | BUCK3_UV_MASK | R/W | 0h | Masking of BUCK3 under-voltage detection interrupt BUCK3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | BUCK3_OV_MASK | R/W | 0h | Masking of BUCK3 over-voltage detection interrupt BUCK3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
MASK_BUCK5 is shown in Figure 8-134 and described in Table 8-94.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK5_ILIM_MASK | RESERVED | BUCK5_UV_MASK | BUCK5_OV_MASK | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R/W | 0h | |
| 3 | BUCK5_ILIM_MASK | R/W | 0h | Masking for BUCK5 current monitoring interrupt BUCK5_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 2 | RESERVED | R/W | 0h | |
| 1 | BUCK5_UV_MASK | R/W | 0h | Masking of BUCK5 under-voltage detection interrupt BUCK5_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | BUCK5_OV_MASK | R/W | 0h | Masking of BUCK5 over-voltage detection interrupt BUCK5_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
MASK_LDO1_2 is shown in Figure 8-135 and described in Table 8-95.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO2_ILIM_MASK | RESERVED | LDO2_UV_MASK | LDO2_OV_MASK | LDO1_ILIM_MASK | RESERVED | LDO1_UV_MASK | LDO1_OV_MASK |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LDO2_ILIM_MASK | R/W | 0h | Masking for LDO2 current monitoring interrupt LDO2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 6 | RESERVED | R/W | 0h | |
| 5 | LDO2_UV_MASK | R/W | 0h | Masking of LDO2 under-voltage detection interrupt LDO2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 4 | LDO2_OV_MASK | R/W | 0h | Masking of LDO2 over-voltage detection interrupt LDO2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 3 | LDO1_ILIM_MASK | R/W | 0h | Masking for LDO1 current monitoring interrupt LDO1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 2 | RESERVED | R/W | 0h | |
| 1 | LDO1_UV_MASK | R/W | 0h | Masking of LDO1 under-voltage detection interrupt LDO1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | LDO1_OV_MASK | R/W | 0h | Masking of LDO1 over-voltage detection interrupt LDO1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
MASK_LDO3_4 is shown in Figure 8-136 and described in Table 8-96.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO4_ILIM_MASK | RESERVED | LDO4_UV_MASK | LDO4_OV_MASK | LDO3_ILIM_MASK | RESERVED | LDO3_UV_MASK | LDO3_OV_MASK |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LDO4_ILIM_MASK | R/W | 0h | Masking for LDO4 current monitoring interrupt LDO4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 6 | RESERVED | R/W | 0h | |
| 5 | LDO4_UV_MASK | R/W | 0h | Masking of LDO4 under-voltage detection interrupt LDO4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 4 | LDO4_OV_MASK | R/W | 0h | Masking of LDO4 over-voltage detection interrupt LDO4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 3 | LDO3_ILIM_MASK | R/W | 0h | Masking for LDO3 current monitoring interrupt LDO3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 2 | RESERVED | R/W | 0h | |
| 1 | LDO3_UV_MASK | R/W | 0h | Masking of LDO3 under-voltage detection interrupt LDO3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | LDO3_OV_MASK | R/W | 0h | Masking of LDO3 over-voltage detection interrupt LDO3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
MASK_VMON is shown in Figure 8-137 and described in Table 8-97.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VCCA_UV_MASK | VCCA_OV_MASK | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | RESERVED | R/W | 0h | |
| 1 | VCCA_UV_MASK | R/W | 0h | Masking of VCCA under-voltage detection interrupt VCCA_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | VCCA_OV_MASK | R/W | 0h | Masking of VCCA over-voltage detection interrupt VCCA_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
MASK_GPIO1_8_FALL is shown in Figure 8-138 and described in Table 8-98.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO8_FALL_MASK | GPIO7_FALL_MASK | GPIO6_FALL_MASK | GPIO5_FALL_MASK | GPIO4_FALL_MASK | GPIO3_FALL_MASK | GPIO2_FALL_MASK | GPIO1_FALL_MASK |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO8_FALL_MASK | R/W | 0h | Masking of interrupt for GPIO8 low state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 6 | GPIO7_FALL_MASK | R/W | 0h | Masking of interrupt for GPIO7 low state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 5 | GPIO6_FALL_MASK | R/W | 0h | Masking of interrupt for GPIO6 low state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 4 | GPIO5_FALL_MASK | R/W | 0h | Masking of interrupt for GPIO5 low state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 3 | GPIO4_FALL_MASK | R/W | 0h | Masking of interrupt for GPIO4 low state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 2 | GPIO3_FALL_MASK | R/W | 0h | Masking of interrupt for GPIO3 low state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 1 | GPIO2_FALL_MASK | R/W | 0h | Masking of interrupt for GPIO2 low state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | GPIO1_FALL_MASK | R/W | 0h | Masking of interrupt for GPIO1 low state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
MASK_GPIO1_8_RISE is shown in Figure 8-139 and described in Table 8-99.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO8_RISE_MASK | GPIO7_RISE_MASK | GPIO6_RISE_MASK | GPIO5_RISE_MASK | GPIO4_RISE_MASK | GPIO3_RISE_MASK | GPIO2_RISE_MASK | GPIO1_RISE_MASK |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO8_RISE_MASK | R/W | 0h | Masking of interrupt for GPIO8 high state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 6 | GPIO7_RISE_MASK | R/W | 0h | Masking of interrupt for GPIO7 high state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 5 | GPIO6_RISE_MASK | R/W | 0h | Masking of interrupt for GPIO6 high state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 4 | GPIO5_RISE_MASK | R/W | 0h | Masking of interrupt for GPIO5 high state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 3 | GPIO4_RISE_MASK | R/W | 0h | Masking of interrupt for GPIO4 high state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 2 | GPIO3_RISE_MASK | R/W | 0h | Masking of interrupt for GPIO3 high state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 1 | GPIO2_RISE_MASK | R/W | 0h | Masking of interrupt for GPIO2 high state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | GPIO1_RISE_MASK | R/W | 0h | Masking of interrupt for GPIO1 high state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
MASK_GPIO9_11 is shown in Figure 8-140 and described in Table 8-100.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GPIO11_RISE_MASK | GPIO10_RISE_MASK | GPIO9_RISE_MASK | GPIO11_FALL_MASK | GPIO10_FALL_MASK | GPIO9_FALL_MASK | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5 | GPIO11_RISE_MASK | R/W | 0h | Masking of interrupt for GPIO11 high state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 4 | GPIO10_RISE_MASK | R/W | 0h | Masking of interrupt for GPIO10 high state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 3 | GPIO9_RISE_MASK | R/W | 0h | Masking of interrupt for GPIO9 high state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 2 | GPIO11_FALL_MASK | R/W | 0h | Masking of interrupt for GPIO11 low state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 1 | GPIO10_FALL_MASK | R/W | 0h | Masking of interrupt for GPIO10 low state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | GPIO9_FALL_MASK | R/W | 0h | Masking of interrupt for GPIO9 low state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
MASK_STARTUP is shown in Figure 8-141 and described in Table 8-101.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SOFT_REBOOT_MASK | FSD_MASK | RESERVED | ENABLE_MASK | NPWRON_START_MASK | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5 | SOFT_REBOOT_MASK | R/W | 0h | Masking of SOFT_REBOOT_MASK interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 4 | FSD_MASK | R/W | 0h | Masking of FSD_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 3-2 | RESERVED | R/W | 0h | |
| 1 | ENABLE_MASK | R/W | 0h | Masking of ENABLE_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | NPWRON_START_MASK | R/W | 0h | Masking of NPWRON_START_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
MASK_MISC is shown in Figure 8-142 and described in Table 8-102.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TWARN_MASK | RESERVED | EXT_CLK_MASK | BIST_PASS_MASK | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R/W | 0h | |
| 3 | TWARN_MASK | R/W | 0h | Masking of TWARN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 2 | RESERVED | R/W | 0h | |
| 1 | EXT_CLK_MASK | R/W | 0h | Masking of EXT_CLK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | BIST_PASS_MASK | R/W | 0h | Masking of BIST_PASS_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
MASK_MODERATE_ERR is shown in Figure 8-143 and described in Table 8-103.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NRSTOUT_READBACK_MASK | NINT_READBACK_MASK | NPWRON_LONG_MASK | SPMI_ERR_MASK | RESERVED | REG_CRC_ERR_MASK | BIST_FAIL_MASK | RESERVED |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | NRSTOUT_READBACK_MASK | R/W | 0h | Masking of NRSTOUT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 6 | NINT_READBACK_MASK | R/W | 0h | Masking of NINT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 5 | NPWRON_LONG_MASK | R/W | 0h | Masking of NPWRON_LONG_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 4 | SPMI_ERR_MASK | R/W | 0h | Masking of SPMI_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 3 | RESERVED | R/W | 0h | |
| 2 | REG_CRC_ERR_MASK | R/W | 0h | Masking of REG_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 1 | BIST_FAIL_MASK | R/W | 0h | Masking of BIST_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | RESERVED | R/W | 0h |
MASK_FSM_ERR is shown in Figure 8-144 and described in Table 8-104.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SOC_PWR_ERR_MASK | MCU_PWR_ERR_MASK | ORD_SHUTDOWN_MASK | IMM_SHUTDOWN_MASK | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R/W | 0h | |
| 3 | SOC_PWR_ERR_MASK | R/W | 0h | Masking of SOC_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 2 | MCU_PWR_ERR_MASK | R/W | 0h | Masking of MCU_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 1 | ORD_SHUTDOWN_MASK | R/W | 0h | Masking of ORD_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | IMM_SHUTDOWN_MASK | R/W | 0h | Masking of IMM_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
MASK_COMM_ERR is shown in Figure 8-145 and described in Table 8-105.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| I2C2_ADR_ERR_MASK | RESERVED | I2C2_CRC_ERR_MASK | RESERVED | COMM_ADR_ERR_MASK | RESERVED | COMM_CRC_ERR_MASK | COMM_FRM_ERR_MASK |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | I2C2_ADR_ERR_MASK | R/W | 0h | Masking of I2C2_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 6 | RESERVED | R/W | 0h | |
| 5 | I2C2_CRC_ERR_MASK | R/W | 0h | Masking of I2C2_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 4 | RESERVED | R/W | 0h | |
| 3 | COMM_ADR_ERR_MASK | R/W | 0h | Masking of COMM_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 2 | RESERVED | R/W | 0h | |
| 1 | COMM_CRC_ERR_MASK | R/W | 0h | Masking of COMM_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | COMM_FRM_ERR_MASK | R/W | 0h | Masking of COMM_FRM_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
MASK_READBACK_ERR is shown in Figure 8-146 and described in Table 8-106.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NRSTOUT_SOC_READBACK_MASK | RESERVED | EN_DRV_READBACK_MASK | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R/W | 0h | |
| 3 | NRSTOUT_SOC_READBACK_MASK | R/W | 0h | Masking of NRSTOUT_SOC_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 2-1 | RESERVED | R/W | 0h | |
| 0 | EN_DRV_READBACK_MASK | R/W | 0h | Masking of EN_DRV_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
MASK_ESM is shown in Figure 8-147 and described in Table 8-107.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ESM_MCU_RST_MASK | ESM_MCU_FAIL_MASK | ESM_MCU_PIN_MASK | ESM_SOC_RST_MASK | ESM_SOC_FAIL_MASK | ESM_SOC_PIN_MASK | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5 | ESM_MCU_RST_MASK | R/W | 0h | Masking of ESM_MCU_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 4 | ESM_MCU_FAIL_MASK | R/W | 0h | Masking of ESM_MCU_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 3 | ESM_MCU_PIN_MASK | R/W | 0h | Masking of ESM_MCU_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 2 | ESM_SOC_RST_MASK | R/W | 0h | Masking of ESM_SOC_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 1 | ESM_SOC_FAIL_MASK | R/W | 0h | Masking of ESM_SOC_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
| 0 | ESM_SOC_PIN_MASK | R/W | 0h | Masking of ESM_SOC_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. |
INT_TOP is shown in Figure 8-148 and described in Table 8-108.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FSM_ERR_INT | SEVERE_ERR_INT | MODERATE_ERR_INT | MISC_INT | STARTUP_INT | GPIO_INT | LDO_VMON_INT | BUCK_INT |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | FSM_ERR_INT | R | 0h | Interrupt indicating that INT_FSM_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_FSM_ERR register. This bit is cleared automatically when INT_FSM_ERR register is cleared to 0x00. |
| 6 | SEVERE_ERR_INT | R | 0h | Interrupt indicating that INT_SEVERE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_SEVERE_ERR register. This bit is cleared automatically when INT_SEVERE_ERR register is cleared to 0x00. |
| 5 | MODERATE_ERR_INT | R | 0h | Interrupt indicating that INT_MODERATE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_MODERATE_ERR register. This bit is cleared automatically when INT_MODERATE_ERR register is cleared to 0x00. |
| 4 | MISC_INT | R | 0h | Interrupt indicating that INT_MISC register has pending interrupt. The reason for the interrupt is indicated in INT_MISC register. This bit is cleared automatically when INT_MISC register is cleared to 0x00. |
| 3 | STARTUP_INT | R | 0h | Interrupt indicating that INT_STARTUP register has pending interrupt. The reason for the interrupt is indicated in INT_STARTUP register. This bit is cleared automatically when INT_STARTUP register is cleared to 0x00. |
| 2 | GPIO_INT | R | 0h | Interrupt indicating that INT_GPIO register has pending interrupt. The reason for the interrupt is indicated in INT_GPIO register. This bit is cleared automatically when INT_GPIO register is cleared to 0x00. |
| 1 | LDO_VMON_INT | R | 0h | Interrupt indicating that INT_LDO_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_LDO_VMON register. This bit is cleared automatically when INT_LDO_VMON register is cleared to 0x00. |
| 0 | BUCK_INT | R | 0h | Interrupt indicating that INT_BUCK register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK register. This bit is cleared automatically when INT_BUCK register is cleared to 0x00. |
INT_BUCK is shown in Figure 8-149 and described in Table 8-109.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK5_INT | BUCK3_4_INT | BUCK1_2_INT | ||||
| R-0h | R-0h | R-0h | R-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-3 | RESERVED | R | 0h | |
| 2 | BUCK5_INT | R | 0h | Interrupt indicating that INT_BUCK5 register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK5 register. This bit is cleared automatically when INT_BUCK5 register is cleared to 0x00. |
| 1 | BUCK3_4_INT | R | 0h | Interrupt indicating that INT_BUCK3_4 register has pending interrupt. This bit is cleared automatically when INT_BUCK3_4 register is cleared to 0x00. |
| 0 | BUCK1_2_INT | R | 0h | Interrupt indicating that INT_BUCK1_2 register has pending interrupt. This bit is cleared automatically when INT_BUCK1_2 register is cleared to 0x00. |
INT_BUCK1_2 is shown in Figure 8-150 and described in Table 8-110.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK2_ILIM_INT | BUCK2_SC_INT | BUCK2_UV_INT | BUCK2_OV_INT | BUCK1_ILIM_INT | BUCK1_SC_INT | BUCK1_UV_INT | BUCK1_OV_INT |
| R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK2_ILIM_INT | R/W1C | 0h | Latched status bit indicating that BUCK2 output current limit has been triggered. Write 1 to clear. |
| 6 | BUCK2_SC_INT | R/W1C | 0h | Latched status bit indicating that the BUCK2 output voltage has fallen below 150 mV level during operation or BUCK2 output didn't reach 150 mV level in TBD us from enable. Write 1 to clear. |
| 5 | BUCK2_UV_INT | R/W1C | 0h | Latched status bit indicating that BUCK2 output under-voltage has been detected. Write 1 to clear. |
| 4 | BUCK2_OV_INT | R/W1C | 0h | Latched status bit indicating that BUCK2 output over-voltage has been detected. Write 1 to clear. |
| 3 | BUCK1_ILIM_INT | R/W1C | 0h | Latched status bit indicating that BUCK1 output current limit has been triggered. Write 1 to clear. |
| 2 | BUCK1_SC_INT | R/W1C | 0h | Latched status bit indicating that the BUCK1 output voltage has fallen below 150 mV level during operation or BUCK1 output didn't reach 150 mV level in TBD us from enable. Write 1 to clear. |
| 1 | BUCK1_UV_INT | R/W1C | 0h | Latched status bit indicating that BUCK1 output under-voltage has been detected. Write 1 to clear. |
| 0 | BUCK1_OV_INT | R/W1C | 0h | Latched status bit indicating that BUCK1 output over-voltage has been detected. Write 1 to clear. |
INT_BUCK3_4 is shown in Figure 8-151 and described in Table 8-111.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_ILIM_INT | BUCK4_SC_INT | BUCK4_UV_INT | BUCK4_OV_INT | BUCK3_ILIM_INT | BUCK3_SC_INT | BUCK3_UV_INT | BUCK3_OV_INT |
| R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK4_ILIM_INT | R/W1C | 0h | Latched status bit indicating that BUCK4 output current limit has been triggered. Write 1 to clear. |
| 6 | BUCK4_SC_INT | R/W1C | 0h | Latched status bit indicating that the BUCK4 output voltage has fallen below 150 mV level during operation or BUCK4 output didn't reach 150 mV level in TBD us from enable. Write 1 to clear. |
| 5 | BUCK4_UV_INT | R/W1C | 0h | Latched status bit indicating that BUCK4 output under-voltage has been detected. Write 1 to clear. |
| 4 | BUCK4_OV_INT | R/W1C | 0h | Latched status bit indicating that BUCK4 output over-voltage has been detected. Write 1 to clear. |
| 3 | BUCK3_ILIM_INT | R/W1C | 0h | Latched status bit indicating that BUCK3 output current limit has been triggered. Write 1 to clear. |
| 2 | BUCK3_SC_INT | R/W1C | 0h | Latched status bit indicating that the BUCK3 output voltage has fallen below 150 mV level during operation or BUCK3 output didn't reach 150 mV level in TBD us from enable. Write 1 to clear. |
| 1 | BUCK3_UV_INT | R/W1C | 0h | Latched status bit indicating that BUCK3 output under-voltage has been detected. Write 1 to clear. |
| 0 | BUCK3_OV_INT | R/W1C | 0h | Latched status bit indicating that BUCK3 output over-voltage has been detected. Write 1 to clear. |
INT_BUCK5 is shown in Figure 8-152 and described in Table 8-112.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK5_ILIM_INT | BUCK5_SC_INT | BUCK5_UV_INT | BUCK5_OV_INT | |||
| R/W-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R/W | 0h | |
| 3 | BUCK5_ILIM_INT | R/W1C | 0h | Latched status bit indicating that BUCK5 output current limit has been triggered. Write 1 to clear. |
| 2 | BUCK5_SC_INT | R/W1C | 0h | Latched status bit indicating that the BUCK5 output voltage has fallen below 150 mV level during operation or BUCK5 output didn't reach 150 mV level in TBD us from enable. Write 1 to clear. |
| 1 | BUCK5_UV_INT | R/W1C | 0h | Latched status bit indicating that BUCK5 output under-voltage has been detected. Write 1 to clear. |
| 0 | BUCK5_OV_INT | R/W1C | 0h | Latched status bit indicating that BUCK5 output over-voltage has been detected. Write 1 to clear. |
INT_LDO_VMON is shown in Figure 8-153 and described in Table 8-113.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VCCA_INT | RESERVED | LDO3_4_INT | LDO1_2_INT | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | RESERVED | R | 0h | |
| 4 | VCCA_INT | R | 0h | Interrupt indicating that INT_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_VMON register. This bit is cleared automatically when INT_VMON register is cleared to 0x00. |
| 3-2 | RESERVED | R | 0h | |
| 1 | LDO3_4_INT | R | 0h | Interrupt indicating that INT_LDO3_4 register has pending interrupt. This bit is cleared automatically when INT_LDO3_4 register is cleared to 0x00. |
| 0 | LDO1_2_INT | R | 0h | Interrupt indicating that INT_LDO1_2 register has pending interrupt. This bit is cleared automatically when INT_LDO1_2 register is cleared to 0x00. |
INT_LDO1_2 is shown in Figure 8-154 and described in Table 8-114.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO2_ILIM_INT | LDO2_SC_INT | LDO2_UV_INT | LDO2_OV_INT | LDO1_ILIM_INT | LDO1_SC_INT | LDO1_UV_INT | LDO1_OV_INT |
| R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LDO2_ILIM_INT | R/W1C | 0h | Latched status bit indicating that LDO2 output current limit has been triggered. Write 1 to clear. |
| 6 | LDO2_SC_INT | R/W1C | 0h | Latched status bit indicating that LDO2 output voltage has fallen below 150 mV level during operation or LDO2 output didn't reach 150 mV level in TBD us from enable. Write 1 to clear. |
| 5 | LDO2_UV_INT | R/W1C | 0h | Latched status bit indicating that LDO2 output under-voltage has been detected. Write 1 to clear. |
| 4 | LDO2_OV_INT | R/W1C | 0h | Latched status bit indicating that LDO2 output over-voltage has been detected. Write 1 to clear. |
| 3 | LDO1_ILIM_INT | R/W1C | 0h | Latched status bit indicating that LDO1 output current limit has been triggered. Write 1 to clear. |
| 2 | LDO1_SC_INT | R/W1C | 0h | Latched status bit indicating that LDO1 output voltage has fallen below 150 mV level during operation or LDO1 output didn't reach 150 mV level in TBD us from enable. Write 1 to clear. |
| 1 | LDO1_UV_INT | R/W1C | 0h | Latched status bit indicating that LDO1 output under-voltage has been detected. Write 1 to clear. |
| 0 | LDO1_OV_INT | R/W1C | 0h | Latched status bit indicating that LDO1 output over-voltage has been detected. Write 1 to clear. |
INT_LDO3_4 is shown in Figure 8-155 and described in Table 8-115.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO4_ILIM_INT | LDO4_SC_INT | LDO4_UV_INT | LDO4_OV_INT | LDO3_ILIM_INT | LDO3_SC_INT | LDO3_UV_INT | LDO3_OV_INT |
| R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LDO4_ILIM_INT | R/W1C | 0h | Latched status bit indicating that LDO4 output current limit has been triggered. Write 1 to clear. |
| 6 | LDO4_SC_INT | R/W1C | 0h | Latched status bit indicating that LDO4 output voltage has fallen below 150 mV level during operation or LDO4 output didn't reach 150 mV level in TBD us from enable. Write 1 to clear. |
| 5 | LDO4_UV_INT | R/W1C | 0h | Latched status bit indicating that LDO4 output under-voltage has been detected. Write 1 to clear. |
| 4 | LDO4_OV_INT | R/W1C | 0h | Latched status bit indicating that LDO4 output over-voltage has been detected. Write 1 to clear. |
| 3 | LDO3_ILIM_INT | R/W1C | 0h | Latched status bit indicating that LDO3 output current limit has been triggered. Write 1 to clear. |
| 2 | LDO3_SC_INT | R/W1C | 0h | Latched status bit indicating that LDO3 output voltage has fallen below 150 mV level during operation or LDO3 output didn't reach 150 mV level in TBD us from enable. Write 1 to clear. |
| 1 | LDO3_UV_INT | R/W1C | 0h | Latched status bit indicating that LDO3 output under-voltage has been detected. Write 1 to clear. |
| 0 | LDO3_OV_INT | R/W1C | 0h | Latched status bit indicating that LDO3 output over-voltage has been detected. Write 1 to clear. |
INT_VMON is shown in Figure 8-156 and described in Table 8-116.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VCCA_UV_INT | VCCA_OV_INT | |||||
| R/W-0h | R/W1C-0h | R/W1C-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | RESERVED | R/W | 0h | |
| 1 | VCCA_UV_INT | R/W1C | 0h | Latched status bit indicating that the VCCA input voltage has decreased below the under-voltage monitoring level. The actual status of the VCCA under-voltage monitoring is indicated by VCCA_UV_STAT bit. Write 1 to clear interrupt. |
| 0 | VCCA_OV_INT | R/W1C | 0h | Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by VCCA_OV_STAT bit. Write 1 to clear interrupt. |
INT_GPIO is shown in Figure 8-157 and described in Table 8-117.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GPIO1_8_INT | GPIO11_INT | GPIO10_INT | GPIO9_INT | |||
| R/W-0h | R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R/W | 0h | |
| 3 | GPIO1_8_INT | R | 0h | Interrupt indicating that INT_GPIO1_8 has pending interrupt. The reason for the interrupt is indicated in INT_GPIO1_8 register. This bit is cleared automatically when INT_GPIO1_8 register is cleared to 0x00. |
| 2 | GPIO11_INT | R/W1C | 0h | Latched status bit indicating that GPIO11 has pending interrupt. GPIO11_IN bit in GPIO_IN_2 register shows the status of the GPIO11 signal. Write 1 to clear interrupt. |
| 1 | GPIO10_INT | R/W1C | 0h | Latched status bit indicating that GPIO10 has pending interrupt. GPIO10_IN bit in GPIO_IN_2 register shows the status of the GPIO10 signal. Write 1 to clear interrupt. |
| 0 | GPIO9_INT | R/W1C | 0h | Latched status bit indicating that GPIO9 has pending interrupt. GPIO9_IN bit in GPIO_IN_2 register shows the status of the GPIO9 signal. Write 1 to clear interrupt. |
INT_GPIO1_8 is shown in Figure 8-158 and described in Table 8-118.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPIO8_INT | GPIO7_INT | GPIO6_INT | GPIO5_INT | GPIO4_INT | GPIO3_INT | GPIO2_INT | GPIO1_INT |
| R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPIO8_INT | R/W1C | 0h | Latched status bit indicating that GPIO8 has has pending interrupt. GPIO8_IN bit in GPIO_IN_1 register shows the status of the GPIO8 signal. Write 1 to clear interrupt. |
| 6 | GPIO7_INT | R/W1C | 0h | Latched status bit indicating that GPIO7 has has pending interrupt. GPIO7_IN bit in GPIO_IN_1 register shows the status of the GPIO7 signal. Write 1 to clear interrupt. |
| 5 | GPIO6_INT | R/W1C | 0h | Latched status bit indicating that GPIO6 has has pending interrupt. GPIO6_IN bit in GPIO_IN_1 register shows the status of the GPIO6 signal. Write 1 to clear interrupt. |
| 4 | GPIO5_INT | R/W1C | 0h | Latched status bit indicating that GPIO5 has has pending interrupt. GPIO5_IN bit in GPIO_IN_1 register shows the status of the GPIO5 signal. Write 1 to clear interrupt. |
| 3 | GPIO4_INT | R/W1C | 0h | Latched status bit indicating that GPIO4 has has pending interrupt. GPIO4_IN bit in GPIO_IN_1 register shows the status of the GPIO4 signal. Write 1 to clear interrupt. |
| 2 | GPIO3_INT | R/W1C | 0h | Latched status bit indicating that GPIO3 has has pending interrupt. GPIO3_IN bit in GPIO_IN_1 register shows the status of the GPIO3 signal. Write 1 to clear interrupt. |
| 1 | GPIO2_INT | R/W1C | 0h | Latched status bit indicating that GPIO2 has pending interrupt. GPIO2_IN bit in GPIO_IN_1 register shows the status of the GPIO2 signal. Write 1 to clear interrupt. |
| 0 | GPIO1_INT | R/W1C | 0h | Latched status bit indicating that GPIO1 has pending interrupt. GPIO1_IN bit in GPIO_IN_1 register shows the status of the GPIO1 signal. Write 1 to clear interrupt. |
INT_STARTUP is shown in Figure 8-159 and described in Table 8-119.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SOFT_REBOOT_INT | FSD_INT | RESERVED | RTC_INT | ENABLE_INT | NPWRON_START_INT | |
| R/W-0h | R/W1C-0h | R/W1C-0h | R/W-0h | R-0h | R/W1C-0h | R/W1C-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5 | SOFT_REBOOT_INT | R/W1C | 0h | Latched status bit indicating that soft reboot event has been detected. Write 1 to clear. |
| 4 | FSD_INT | R/W1C | 0h | Latched status bit indicating that PMIC has started from NO_SUPPLY or BACKUP state (first supply dectection). Write 1 to clear. |
| 3 | RESERVED | R/W | 0h | |
| 2 | RTC_INT | R | 0h | Latched status bit indicating that RTC_STATUS register has pending interrupt. This bit is cleared automatically when ALARM and TIMER interrupts are cleared. |
| 1 | ENABLE_INT | R/W1C | 0h | Latched status bit indicating that ENABLE pin active event has been detected. Write 1 to clear. |
| 0 | NPWRON_START_INT | R/W1C | 0h | Latched status bit indicating that NPWRON start-up event has been detected. Write 1 to clear. |
INT_MISC is shown in Figure 8-160 and described in Table 8-120.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TWARN_INT | RESERVED | EXT_CLK_INT | BIST_PASS_INT | |||
| R/W-0h | R/W1C-0h | R/W-0h | R/W1C-0h | R/W1C-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R/W | 0h | |
| 3 | TWARN_INT | R/W1C | 0h | Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TWARN_STAT bit in STAT_MISC register. Write 1 to clear interrupt. |
| 2 | RESERVED | R/W | 0h | |
| 1 | EXT_CLK_INT | R/W1C | 0h | Latched status bit indicating that external clock is not valid. Internal clock is automatically taken into use. Write 1 to clear. |
| 0 | BIST_PASS_INT | R/W1C | 0h | Latched status bit indicating that BIST has been completed. Write 1 to clear interrupt. |
INT_MODERATE_ERR is shown in Figure 8-161 and described in Table 8-121.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NRSTOUT_READBACK_INT | NINT_READBACK_INT | NPWRON_LONG_INT | SPMI_ERR_INT | RECOV_CNT_INT | REG_CRC_ERR_INT | BIST_FAIL_INT | TSD_ORD_INT |
| R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | NRSTOUT_READBACK_INT | R/W1C | 0h | Latched status bit indicating that NRSTOUT readback error has been detected. Write 1 to clear interrupt. |
| 6 | NINT_READBACK_INT | R/W1C | 0h | Latched status bit indicating that NINT readback error has been detected. Write 1 to clear interrupt. |
| 5 | NPWRON_LONG_INT | R/W1C | 0h | Latched status bit indicating that NPWRON long press has been detected. Write 1 to clear. |
| 4 | SPMI_ERR_INT | R/W1C | 0h | Latched status bit indicating that the SPMI communication interface has detected an error. Write 1 to clear interrupt. |
| 3 | RECOV_CNT_INT | R/W1C | 0h | Latched status bit indicating that RECOV_CNT has reached the limit (RECOV_CNT_THR). Write 1 to clear. |
| 2 | REG_CRC_ERR_INT | R/W1C | 0h | Latched status bit indicating that the register CRC checking has detected an error. Write 1 to clear interrupt. |
| 1 | BIST_FAIL_INT | R/W1C | 0h | Latched status bit indicating that the LBIST or ABIST has detected an error. Write 1 to clear interrupt. |
| 0 | TSD_ORD_INT | R/W1C | 0h | Latched status bit indicating that the die junction temperature has exceeded the thermal level causing a sequenced shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_ORD_STAT bit in STAT_MODERATE_ERR register. Write 1 to clear interrupt. |
INT_SEVERE_ERR is shown in Figure 8-162 and described in Table 8-122.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PFSM_ERR_INT | VCCA_OVP_INT | TSD_IMM_INT | ||||
| R/W-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-3 | RESERVED | R/W | 0h | |
| 2 | PFSM_ERR_INT | R/W1C | 0h | Latched status bit indicating that the PFSM sequencer has detected an error. Write 1 to clear interrupt. |
| 1 | VCCA_OVP_INT | R/W1C | 0h | Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage threshold level causing an immediate shutdown. The regulators have been disabled. Write 1 to clear interrupt. |
| 0 | TSD_IMM_INT | R/W1C | 0h | Latched status bit indicating that the die junction temperature has exceeded the thermal level causing an immediate shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_IMM_STAT bit in THER_CLK_STATUS register. Write 1 to clear interrupt. |
INT_FSM_ERR is shown in Figure 8-163 and described in Table 8-123.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WD_INT | ESM_INT | READBACK_ERR_INT | COMM_ERR_INT | SOC_PWR_ERR_INT | MCU_PWR_ERR_INT | ORD_SHUTDOWN_INT | IMM_SHUTDOWN_INT |
| R-0h | R-0h | R-0h | R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | WD_INT | R | 0h | Interrupt indicating that WD_ERR_STATUS register has pending interrupt. This bit is cleared automatically when WD_RST_INT, WD_FAIL_INT and WD_LONGWIN_TIMEOUT_INT are cleared. |
| 6 | ESM_INT | R | 0h | Interrupt indicating that INT_ESM has pending interrupt. This bit is cleared automatically when INT_ESM register is cleared to 0x00. |
| 5 | READBACK_ERR_INT | R | 0h | Interrupt indicating that INT_READBACK_ERR has pending interrupt. This bit is cleared automatically when INT_READBACK_ERR register is cleared to 0x00. |
| 4 | COMM_ERR_INT | R | 0h | Interrupt indicating that INT_COMM_ERR has pending interrupt. The reason for the interrupt is indicated in INT_COMM_ERR register. This bit is cleared automatically when INT_COMM_ERR register is cleared to 0x00. |
| 3 | SOC_PWR_ERR_INT | R/W1C | 0h | Latched status bit indicating that SOC power error has been detected. Write 1 to clear. |
| 2 | MCU_PWR_ERR_INT | R/W1C | 0h | Latched status bit indicating that MCU power error has been detected. Write 1 to clear. |
| 1 | ORD_SHUTDOWN_INT | R/W1C | 0h | Latched status bit indicating that orderly shutdown has been detected. Write 1 to clear. |
| 0 | IMM_SHUTDOWN_INT | R/W1C | 0h | Latched status bit indicating that immediate shutdown has been detected. Write 1 to clear. |
INT_COMM_ERR is shown in Figure 8-164 and described in Table 8-124.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| I2C2_ADR_ERR_INT | RESERVED | I2C2_CRC_ERR_INT | RESERVED | COMM_ADR_ERR_INT | RESERVED | COMM_CRC_ERR_INT | COMM_FRM_ERR_INT |
| R/W1C-0h | R/W-0h | R/W1C-0h | R/W-0h | R/W1C-0h | R/W-0h | R/W1C-0h | R/W1C-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | I2C2_ADR_ERR_INT | R/W1C | 0h | Latched status bit indicating that I2C2 write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. |
| 6 | RESERVED | R/W | 0h | |
| 5 | I2C2_CRC_ERR_INT | R/W1C | 0h | Latched status bit indicating that I2C2 CRC error has been detected. Write 1 to clear interrupt. |
| 4 | RESERVED | R/W | 0h | |
| 3 | COMM_ADR_ERR_INT | R/W1C | 0h | Latched status bit indicating that I2C1/SPI write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. |
| 2 | RESERVED | R/W | 0h | |
| 1 | COMM_CRC_ERR_INT | R/W1C | 0h | Latched status bit indicating that I2C1/SPI CRC error has been detected. Write 1 to clear interrupt. |
| 0 | COMM_FRM_ERR_INT | R/W1C | 0h | Latched status bit indicating that SPI frame error has been detected. Write 1 to clear interrupt. |
INT_READBACK_ERR is shown in Figure 8-165 and described in Table 8-125.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NRSTOUT_SOC_READBACK_INT | RESERVED | EN_DRV_READBACK_INT | ||||
| R/W-0h | R/W1C-0h | R/W-0h | R/W1C-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R/W | 0h | |
| 3 | NRSTOUT_SOC_READBACK_INT | R/W1C | 0h | Latched status bit indicating that NRSTOUT_SOC readback error has been detected. Write 1 to clear interrupt. |
| 2-1 | RESERVED | R/W | 0h | |
| 0 | EN_DRV_READBACK_INT | R/W1C | 0h | Latched status bit indicating that EN_DRV readback error has been detected. Write 1 to clear interrupt. |
INT_ESM is shown in Figure 8-166 and described in Table 8-126.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ESM_MCU_RST_INT | ESM_MCU_FAIL_INT | ESM_MCU_PIN_INT | ESM_SOC_RST_INT | ESM_SOC_FAIL_INT | ESM_SOC_PIN_INT | |
| R/W-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5 | ESM_MCU_RST_INT | R/W1C | 0h | Latched status bit indicating that MCU ESM reset has been detected. Write 1 to clear interrupt. |
| 4 | ESM_MCU_FAIL_INT | R/W1C | 0h | Latched status bit indicating that MCU ESM fail has been detected. Write 1 to clear interrupt. |
| 3 | ESM_MCU_PIN_INT | R/W1C | 0h | Latched status bit indicating that MCU ESM fault has been detected. Write 1 to clear interrupt. |
| 2 | ESM_SOC_RST_INT | R/W1C | 0h | Latched status bit indicating that SOC ESM reset has been detected. Write 1 to clear interrupt. |
| 1 | ESM_SOC_FAIL_INT | R/W1C | 0h | Latched status bit indicating that SOC ESM fail has been detected. Write 1 to clear interrupt. |
| 0 | ESM_SOC_PIN_INT | R/W1C | 0h | Latched status bit indicating that SOC ESM fault has been detected. Write 1 to clear interrupt. |
STAT_BUCK1_2 is shown in Figure 8-167 and described in Table 8-127.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK2_ILIM_STAT | RESERVED | BUCK2_UV_STAT | BUCK2_OV_STAT | BUCK1_ILIM_STAT | RESERVED | BUCK1_UV_STAT | BUCK1_OV_STAT |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK2_ILIM_STAT | R | 0h | Status bit indicating that BUCK2 output current is above current limit level. |
| 6 | RESERVED | R | 0h | |
| 5 | BUCK2_UV_STAT | R | 0h | Status bit indicating that BUCK2 output voltage is below under-voltage threshold. |
| 4 | BUCK2_OV_STAT | R | 0h | Status bit indicating that BUCK2 output voltage is above over-voltage threshold. |
| 3 | BUCK1_ILIM_STAT | R | 0h | Status bit indicating that BUCK1 output current is above current limit level. |
| 2 | RESERVED | R | 0h | |
| 1 | BUCK1_UV_STAT | R | 0h | Status bit indicating that BUCK1 output voltage is below under-voltage threshold. |
| 0 | BUCK1_OV_STAT | R | 0h | Status bit indicating that BUCK1 output voltage is above over-voltage threshold. |
STAT_BUCK3_4 is shown in Figure 8-168 and described in Table 8-128.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUCK4_ILIM_STAT | RESERVED | BUCK4_UV_STAT | BUCK4_OV_STAT | BUCK3_ILIM_STAT | RESERVED | BUCK3_UV_STAT | BUCK3_OV_STAT |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUCK4_ILIM_STAT | R | 0h | Status bit indicating that BUCK4 output current is above current limit level. |
| 6 | RESERVED | R | 0h | |
| 5 | BUCK4_UV_STAT | R | 0h | Status bit indicating that BUCK4 output voltage is below under-voltage threshold. |
| 4 | BUCK4_OV_STAT | R | 0h | Status bit indicating that BUCK4 output voltage is above over-voltage threshold. |
| 3 | BUCK3_ILIM_STAT | R | 0h | Status bit indicating that BUCK3 output current is above current limit level. |
| 2 | RESERVED | R | 0h | |
| 1 | BUCK3_UV_STAT | R | 0h | Status bit indicating that BUCK3 output voltage is below under-voltage threshold. |
| 0 | BUCK3_OV_STAT | R | 0h | Status bit indicating that BUCK3 output voltage is above over-voltage threshold. |
STAT_BUCK5 is shown in Figure 8-169 and described in Table 8-129.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK5_ILIM_STAT | RESERVED | BUCK5_UV_STAT | BUCK5_OV_STAT | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R | 0h | |
| 3 | BUCK5_ILIM_STAT | R | 0h | Status bit indicating that BUCK5 output current is above current limit level. |
| 2 | RESERVED | R | 0h | |
| 1 | BUCK5_UV_STAT | R | 0h | Status bit indicating that BUCK5 output voltage is below under-voltage threshold. |
| 0 | BUCK5_OV_STAT | R | 0h | Status bit indicating that BUCK5 output voltage is above over-voltage threshold. |
STAT_LDO1_2 is shown in Figure 8-170 and described in Table 8-130.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO2_ILIM_STAT | RESERVED | LDO2_UV_STAT | LDO2_OV_STAT | LDO1_ILIM_STAT | RESERVED | LDO1_UV_STAT | LDO1_OV_STAT |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LDO2_ILIM_STAT | R | 0h | Status bit indicating that LDO2 output current is above current limit level. |
| 6 | RESERVED | R | 0h | |
| 5 | LDO2_UV_STAT | R | 0h | Status bit indicating that LDO2 output voltage is below under-voltage threshold. |
| 4 | LDO2_OV_STAT | R | 0h | Status bit indicating that LDO2 output voltage is above over-voltage threshold. |
| 3 | LDO1_ILIM_STAT | R | 0h | Status bit indicating that LDO1 output current is above current limit level. |
| 2 | RESERVED | R | 0h | |
| 1 | LDO1_UV_STAT | R | 0h | Status bit indicating that LDO1 output voltage is below under-voltage threshold. |
| 0 | LDO1_OV_STAT | R | 0h | Status bit indicating that LDO1 output voltage is above over-voltage threshold. |
STAT_LDO3_4 is shown in Figure 8-171 and described in Table 8-131.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO4_ILIM_STAT | RESERVED | LDO4_UV_STAT | LDO4_OV_STAT | LDO3_ILIM_STAT | RESERVED | LDO3_UV_STAT | LDO3_OV_STAT |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LDO4_ILIM_STAT | R | 0h | Status bit indicating that LDO4 output current is above current limit level. |
| 6 | RESERVED | R | 0h | |
| 5 | LDO4_UV_STAT | R | 0h | Status bit indicating that LDO4 output voltage is below under-voltage threshold. |
| 4 | LDO4_OV_STAT | R | 0h | Status bit indicating that LDO4 output voltage is above over-voltage threshold. |
| 3 | LDO3_ILIM_STAT | R | 0h | Status bit indicating that LDO3 output current is above current limit level. |
| 2 | RESERVED | R | 0h | |
| 1 | LDO3_UV_STAT | R | 0h | Status bit indicating that LDO3 output voltage is below under-voltage threshold. |
| 0 | LDO3_OV_STAT | R | 0h | Status bit indicating that LDO3 output voltage is above over-voltage threshold. |
STAT_VMON is shown in Figure 8-172 and described in Table 8-132.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VCCA_UV_STAT | VCCA_OV_STAT | |||||
| R-0h | R-0h | R-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | RESERVED | R | 0h | |
| 1 | VCCA_UV_STAT | R | 0h | Status bit indicating that VCCA input voltage is below under-voltage level. |
| 0 | VCCA_OV_STAT | R | 0h | Status bit indicating that VCCA input voltage is above over-voltage level. |
STAT_STARTUP is shown in Figure 8-173 and described in Table 8-133.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ENABLE_STAT | RESERVED | |||||
| R-0h | R-0h | R-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | RESERVED | R | 0h | |
| 1 | ENABLE_STAT | R | 0h | Status bit indicating nPWRON / EN pin status |
| 0 | RESERVED | R | 0h |
STAT_MISC is shown in Figure 8-174 and described in Table 8-134.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TWARN_STAT | RESERVED | EXT_CLK_STAT | RESERVED | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R | 0h | |
| 3 | TWARN_STAT | R | 0h | Status bit indicating that die junction temperature is above the thermal warning level. |
| 2 | RESERVED | R | 0h | |
| 1 | EXT_CLK_STAT | R | 0h | Status bit indicating that external clock is not valid. |
| 0 | RESERVED | R | 0h |
STAT_MODERATE_ERR is shown in Figure 8-175 and described in Table 8-135.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TSD_ORD_STAT | ||||||
| R-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-1 | RESERVED | R | 0h | |
| 0 | TSD_ORD_STAT | R | 0h | Status bit indicating that the die junction temperature is above the thermal level causing a sequenced shutdown. |
STAT_SEVERE_ERR is shown in Figure 8-176 and described in Table 8-136.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VCCA_OVP_STAT | TSD_IMM_STAT | |||||
| R-0h | R-0h | R-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | RESERVED | R | 0h | |
| 1 | VCCA_OVP_STAT | R | 0h | Status bit indicating that the VCCA voltage is above overvoltage protection level. |
| 0 | TSD_IMM_STAT | R | 0h | Status bit indicating that the die junction temperature is above the thermal level causing an immediate shutdown. |
STAT_READBACK_ERR is shown in Figure 8-177 and described in Table 8-137.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NRSTOUT_SOC_READBACK_STAT | NRSTOUT_READBACK_STAT | NINT_READBACK_STAT | EN_DRV_READBACK_STAT | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R | 0h | |
| 3 | NRSTOUT_SOC_READBACK_STAT | R | 0h | Status bit indicating that NRSTOUT_SOC pin output is high and device is driving it low. |
| 2 | NRSTOUT_READBACK_STAT | R | 0h | Status bit indicating that NRSTOUT pin output is high and device is driving it low. |
| 1 | NINT_READBACK_STAT | R | 0h | Status bit indicating that NINT pin output is high and device is driving it low. |
| 0 | EN_DRV_READBACK_STAT | R | 0h | Status bit indicating that EN_DRV pin output is different than driven. |
PGOOD_SEL_1 is shown in Figure 8-178 and described in Table 8-138.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PGOOD_SEL_BUCK4 | PGOOD_SEL_BUCK3 | PGOOD_SEL_BUCK2 | PGOOD_SEL_BUCK1 | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | PGOOD_SEL_BUCK4 | R/W | 0h | PGOOD signal source control from BUCK4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit |
| 5-4 | PGOOD_SEL_BUCK3 | R/W | 0h | PGOOD signal source control from BUCK3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit |
| 3-2 | PGOOD_SEL_BUCK2 | R/W | 0h | PGOOD signal source control from BUCK2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit |
| 1-0 | PGOOD_SEL_BUCK1 | R/W | 0h | PGOOD signal source control from BUCK1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit |
PGOOD_SEL_2 is shown in Figure 8-179 and described in Table 8-139.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PGOOD_SEL_BUCK5 | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | RESERVED | R/W | 0h | |
| 1-0 | PGOOD_SEL_BUCK5 | R/W | 0h | PGOOD signal source control from BUCK5 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit |
PGOOD_SEL_3 is shown in Figure 8-180 and described in Table 8-140.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PGOOD_SEL_LDO4 | PGOOD_SEL_LDO3 | PGOOD_SEL_LDO2 | PGOOD_SEL_LDO1 | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | PGOOD_SEL_LDO4 | R/W | 0h | PGOOD signal source control from LDO4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit |
| 5-4 | PGOOD_SEL_LDO3 | R/W | 0h | PGOOD signal source control from LDO3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit |
| 3-2 | PGOOD_SEL_LDO2 | R/W | 0h | PGOOD signal source control from LDO2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit |
| 1-0 | PGOOD_SEL_LDO1 | R/W | 0h | PGOOD signal source control from LDO1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit |
PGOOD_SEL_4 is shown in Figure 8-181 and described in Table 8-141.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PGOOD_WINDOW | PGOOD_POL | PGOOD_SEL_NRSTOUT_SOC | PGOOD_SEL_NRSTOUT | PGOOD_SEL_TDIE_WARN | RESERVED | PGOOD_SEL_VCCA | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | PGOOD_WINDOW | R/W | 0h | Type of voltage monitoring for PGOOD signal: (Default from NVM memory) 0h = Only undervoltage is monitored 1h = Both undervoltage and overvoltage are monitored |
| 6 | PGOOD_POL | R/W | 0h | PGOOD signal polarity select: (Default from NVM memory) 0h = PGOOD signal is high when monitored inputs are valid 1h = PGOOD signal is low when monitored inputs are valid |
| 5 | PGOOD_SEL_NRSTOUT_SOC | R/W | 0h | PGOOD signal source control from nRSTOUT_SOC pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT_SOC pin low state forces PGOOD signal to low |
| 4 | PGOOD_SEL_NRSTOUT | R/W | 0h | PGOOD signal source control from nRSTOUT pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT pin low state forces PGOOD signal to low |
| 3 | PGOOD_SEL_TDIE_WARN | R/W | 0h | PGOOD signal source control from thermal warning (Default from NVM memory) 0h = Masked 1h = Thermal warning affecting to PGOOD signal |
| 2-1 | RESERVED | R/W | 0h | |
| 0 | PGOOD_SEL_VCCA | R/W | 0h | PGOOD signal source control from VCCA monitoring (Default from NVM memory) 0h = Masked 1h = VCCA OV/UV threshold affecting PGOOD signal |
PLL_CTRL is shown in Figure 8-182 and described in Table 8-142.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EXT_CLK_FREQ | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | RESERVED | R/W | 0h | |
| 1-0 | EXT_CLK_FREQ | R/W | 0h | Frequency of the external clock (SYNCCLKIN): See electrical specification for input clock frequency tolerance. (Default from NVM memory) 0h = 1.1 MHz 1h = 2.2 MHz 2h = 4.4 MHz 3h = Reserved |
CONFIG_1 is shown in Figure 8-183 and described in Table 8-143.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NSLEEP2_MASK | NSLEEP1_MASK | EN_ILIM_FSM_CTRL | I2C2_HS | I2C1_HS | RESERVED | TSD_ORD_LEVEL | TWARN_LEVEL |
| R/W-1h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | NSLEEP2_MASK | R/W | 1h | Masking for NSLEEP2 pin(s) and NSLEEP2B bit: (Default from NVM memory) 0h = NSLEEP2(B) affects FSM state transitions. 1h = NSLEEP2(B) does not affect FSM state transitions. |
| 6 | NSLEEP1_MASK | R/W | 1h | Masking for NSLEEP1 pin(s) and NSLEEP1B bit: (Default from NVM memory) 0h = NSLEEP1(B) affects FSM state transitions. 1h = NSLEEP1(B) does not affect FSM state transitions. |
| 5 | EN_ILIM_FSM_CTRL | R/W | 0h | (Default from NVM memory)
0h = Buck/LDO regulators ILIM interrupts do not affect FSM triggers. 1h = Buck/LDO regulators ILIM interrupts affect FSM triggers. |
| 4 | I2C2_HS | R/W | 0h | Select I2C2 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode |
| 3 | I2C1_HS | R/W | 0h | Select I2C1 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode |
| 2 | RESERVED | R/W | 0h | |
| 1 | TSD_ORD_LEVEL | R/W | 0h | Thermal shutdown threshold level. (Default from NVM memory) 0h = 140C 1h = 145C |
| 0 | TWARN_LEVEL | R/W | 0h | Thermal warning threshold level. (Default from NVM memory) 0h = 130C 1h = 140C |
CONFIG_2 is shown in Figure 8-184 and described in Table 8-144.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BB_EOC_RDY | RESERVED | BB_VEOC | BB_ICHR | BB_CHARGER_EN | |||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BB_EOC_RDY | R | 0h | Backup end of charge indication
0h = Charging active or not enabled 1h = Charger has reached termination voltage set by BB_VEOC register |
| 6-4 | RESERVED | R/W | 0h | |
| 3-2 | BB_VEOC | R/W | 0h | End of charge voltage for backup battery charger: (Default from NVM memory) 0h = 2.5V 1h = 2.8V 2h = 3.0V 3h = 3.3V |
| 1 | BB_ICHR | R/W | 0h | Backup battery charging current: (Default from NVM memory) 0h = 100uA 1h = 500uA |
| 0 | BB_CHARGER_EN | R/W | 0h | Backup battery charging:
0h = Disabled 1h = Enabled |
ENABLE_DRV_REG is shown in Figure 8-185 and described in Table 8-145.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ENABLE_DRV | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-1 | RESERVED | R/W | 0h | |
| 0 | ENABLE_DRV | R/W | 0h | Control for EN_DRV pin: FORCE_EN_DRV_LOW must be 0 to control EN_DRV pin. Otherwise EN_DRV pin is low. 0h = Low 1h = High |
MISC_CTRL is shown in Figure 8-186 and described in Table 8-146.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SYNCCLKOUT_FREQ_SEL | SEL_EXT_CLK | AMUXOUT_EN | CLKMON_EN | LPM_EN | NRSTOUT_SOC | NRSTOUT | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | SYNCCLKOUT_FREQ_SEL | R/W | 0h | SYNCCLKOUT enable/frequency select:
0h = SYNCCLKOUT off 1h = 1.1 MHz 2h = 2.2 MHz 3h = 4.4 MHz |
| 5 | SEL_EXT_CLK | R/W | 0h | Selection of external clock:
0h = Forced to internal RC oscillator. 1h = Automatic external clock used when available, interrupt is generated if the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. |
| 4 | AMUXOUT_EN | R/W | 0h | Control bandgap voltage to AMUXOUT pin.
0h = Disabled 1h = Enabled |
| 3 | CLKMON_EN | R/W | 0h | Control of internal clock monitoring.
0h = Disabled 1h = Enabled |
| 2 | LPM_EN | R/W | 0h | Low power mode control. LPM_EN sets device in a low power mode. Intended use case is for the PFSM to set LPM_EN upon entering a deep sleep state. The end objective is to disable the digital oscillator to reduce power consumption. The following functions are disabled when LPM_EN=1. -TSD cycling of all sensors/thresholds -regmap/SRAM CRC continuous checking -SPMI WD NVM_ID request/response polling -Disable clock monitoring 0h = Low power mode disabled 1h = Low power mode enabled |
| 1 | NRSTOUT_SOC | R/W | 0h | Control for nRSTOUT_SOC signal:
0h = Low 1h = High |
| 0 | NRSTOUT | R/W | 0h | Control for nRSTOUT signal:
0h = Low 1h = High |
ENABLE_DRV_STAT is shown in Figure 8-187 and described in Table 8-147.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SPMI_LPM_EN | FORCE_EN_DRV_LOW | NRSTOUT_SOC_IN | NRSTOUT_IN | EN_DRV_IN | ||
| R/W-0h | R/W-0h | R/W-1h | R-0h | R-0h | R-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | RESERVED | R/W | 0h | |
| 4 | SPMI_LPM_EN | R/W | 0h | This bit is read/write for PFSM and read-only for I2C/SPI SPMI low power mode control. SPMI_LPM_EN sets SPMI in a low power mode which stops SPMI WD (Bus heartbeat). PMICs enters SPMI_LPM_EN=1 at similar times to prevent SPMI WD failures. Therefore to mitigate clock variations, setting SPMI_LPM_EN=1 must be done early in the sequence. The following functions are disabled when SPMI_LPM_EN=1. -SPMI WD NVM_ID request/response polling 0h = SPMI low power mode disabled 1h = SPMI low power mode enabled |
| 3 | FORCE_EN_DRV_LOW | R/W | 1h | This bit is read/write for PFSM and read-only for I2C/SPI
0h = ENABLE_DRV bit can be written by I2C/SPI 1h = ENABLE_DRV bit is forced low and cannot be written high by I2C/SPI |
| 2 | NRSTOUT_SOC_IN | R | 0h | Level of NRSTOUT_SOC pin:
0h = Low 1h = High |
| 1 | NRSTOUT_IN | R | 0h | Level of NRSTOUT pin:
0h = Low 1h = High |
| 0 | EN_DRV_IN | R | 0h | Level of EN_DRV pin:
0h = Low 1h = High |
RECOV_CNT_REG_1 is shown in Figure 8-188 and described in Table 8-148.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RECOV_CNT | ||||||
| R-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R | 0h | |
| 3-0 | RECOV_CNT | R | 0h | Recovery counter status. Counter value is incremented each time PMIC goes through warm reset. |
RECOV_CNT_REG_2 is shown in Figure 8-189 and described in Table 8-149.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RECOV_CNT_CLR | RECOV_CNT_THR | |||||
| R/W-0h | R/WSelfClrF-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | RESERVED | R/W | 0h | |
| 4 | RECOV_CNT_CLR | R/WSelfClrF | 0h | Recovery counter clear. Write 1 to clear the counter. This bit is automatically set back to 0. |
| 3-0 | RECOV_CNT_THR | R/W | 0h | Recovery counter threshold value for immediate power-down of all supply rails. (Default from NVM memory) |
FSM_I2C_TRIGGERS is shown in Figure 8-190 and described in Table 8-150.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TRIGGER_I2C_7 | TRIGGER_I2C_6 | TRIGGER_I2C_5 | TRIGGER_I2C_4 | TRIGGER_I2C_3 | TRIGGER_I2C_2 | TRIGGER_I2C_1 | TRIGGER_I2C_0 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/WSelfClrF-0h | R/WSelfClrF-0h | R/WSelfClrF-0h | R/WSelfClrF-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | TRIGGER_I2C_7 | R/W | 0h | Trigger for PFSM program. |
| 6 | TRIGGER_I2C_6 | R/W | 0h | Trigger for PFSM program. |
| 5 | TRIGGER_I2C_5 | R/W | 0h | Trigger for PFSM program. |
| 4 | TRIGGER_I2C_4 | R/W | 0h | Trigger for PFSM program. |
| 3 | TRIGGER_I2C_3 | R/WSelfClrF | 0h | Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. |
| 2 | TRIGGER_I2C_2 | R/WSelfClrF | 0h | Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. |
| 1 | TRIGGER_I2C_1 | R/WSelfClrF | 0h | Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. |
| 0 | TRIGGER_I2C_0 | R/WSelfClrF | 0h | Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. |
FSM_NSLEEP_TRIGGERS is shown in Figure 8-191 and described in Table 8-151.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NSLEEP2B | NSLEEP1B | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | RESERVED | R/W | 0h | |
| 1 | NSLEEP2B | R/W | 0h | Parallel register bit for NSLEEP2 function:
0h = NSLEEP2 low 1h = NSLEEP2 high |
| 0 | NSLEEP1B | R/W | 0h | Parallel register bit for NSLEEP1 function:
0h = NSLEEP1 low 1h = NSLEEP1 high |
BUCK_RESET_REG is shown in Figure 8-192 and described in Table 8-152.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK5_RESET | BUCK4_RESET | BUCK3_RESET | BUCK2_RESET | BUCK1_RESET | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | RESERVED | R/W | 0h | |
| 4 | BUCK5_RESET | R/W | 0h | Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO "1" DURING DEVICE OPERATION. |
| 3 | BUCK4_RESET | R/W | 0h | Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO "1" DURING DEVICE OPERATION. |
| 2 | BUCK3_RESET | R/W | 0h | Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO "1" DURING DEVICE OPERATION. |
| 1 | BUCK2_RESET | R/W | 0h | Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO "1" DURING DEVICE OPERATION. |
| 0 | BUCK1_RESET | R/W | 0h | Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO "1" DURING DEVICE OPERATION. |
SPREAD_SPECTRUM_1 is shown in Figure 8-193 and described in Table 8-153.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SS_EN | SS_DEPTH | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-3 | RESERVED | R/W | 0h | |
| 2 | SS_EN | R/W | 0h | Spread spectrum enable. (Default from NVM memory) 0h = Spread spectrum disabled 1h = Spread spectrum enabled |
| 1-0 | SS_DEPTH | R/W | 0h | Spread spectrum modulation depth. (Default from NVM memory) 0h = No modulation 1h = +/- 6.3% 2h = +/- 8.4% 3h = RESERVED |
FREQ_SEL is shown in Figure 8-194 and described in Table 8-154.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUCK5_FREQ_SEL | BUCK4_FREQ_SEL | BUCK3_FREQ_SEL | BUCK2_FREQ_SEL | BUCK1_FREQ_SEL | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | RESERVED | R/W | 0h | |
| 4 | BUCK5_FREQ_SEL | R/W | 0h | Buck5 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz |
| 3 | BUCK4_FREQ_SEL | R/W | 0h | Buck4 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz |
| 2 | BUCK3_FREQ_SEL | R/W | 0h | Buck3 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz |
| 1 | BUCK2_FREQ_SEL | R/W | 0h | Buck2 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz |
| 0 | BUCK1_FREQ_SEL | R/W | 0h | Buck1 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz |
FSM_STEP_SIZE is shown in Figure 8-195 and described in Table 8-155.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PFSM_DELAY_STEP | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | RESERVED | R/W | 0h | |
| 4-0 | PFSM_DELAY_STEP | R/W | 0h | Step size for PFSM sequence counter. Step size is 50ns * 2PFSM_DELAY_STEP. (Default from NVM memory) |
LDO_RV_TIMEOUT_REG_1 is shown in Figure 8-196 and described in Table 8-156.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO2_RV_TIMEOUT | LDO1_RV_TIMEOUT | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | LDO2_RV_TIMEOUT | R/W | 0h | LDO residual voltage check timeout select. (Default from NVM memory) 0h = 0.5ms 1h = 1ms 2h = 1.5ms 3h = 2ms 4h = 2.5ms 5h = 3ms 6h = 3.5ms 7h = 4ms 8h = 2ms 9h = 4ms Ah = 6ms Bh = 8ms Ch = 10ms Dh = 12ms Eh = 14ms Fh = 16ms |
| 3-0 | LDO1_RV_TIMEOUT | R/W | 0h | LDO residual voltage check timeout select. (Default from NVM memory) 0h = 0.5ms 1h = 1ms 2h = 1.5ms 3h = 2ms 4h = 2.5ms 5h = 3ms 6h = 3.5ms 7h = 4ms 8h = 2ms 9h = 4ms Ah = 6ms Bh = 8ms Ch = 10ms Dh = 12ms Eh = 14ms Fh = 16ms |
LDO_RV_TIMEOUT_REG_2 is shown in Figure 8-197 and described in Table 8-157.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LDO4_RV_TIMEOUT | LDO3_RV_TIMEOUT | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | LDO4_RV_TIMEOUT | R/W | 0h | LDO residual voltage check timeout select. (Default from NVM memory) 0h = 0.5ms 1h = 1ms 2h = 1.5ms 3h = 2ms 4h = 2.5ms 5h = 3ms 6h = 3.5ms 7h = 4ms 8h = 2ms 9h = 4ms Ah = 6ms Bh = 8ms Ch = 10ms Dh = 12ms Eh = 14ms Fh = 16ms |
| 3-0 | LDO3_RV_TIMEOUT | R/W | 0h | LDO residual voltage check timeout select. (Default from NVM memory) 0h = 0.5ms 1h = 1ms 2h = 1.5ms 3h = 2ms 4h = 2.5ms 5h = 3ms 6h = 3.5ms 7h = 4ms 8h = 2ms 9h = 4ms Ah = 6ms Bh = 8ms Ch = 10ms Dh = 12ms Eh = 14ms Fh = 16ms |
USER_SPARE_REGS is shown in Figure 8-198 and described in Table 8-158.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | USER_SPARE_4 | USER_SPARE_3 | USER_SPARE_2 | USER_SPARE_1 | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R/W | 0h | |
| 3 | USER_SPARE_4 | R/W | 0h | (Default from NVM memory) |
| 2 | USER_SPARE_3 | R/W | 0h | (Default from NVM memory) |
| 1 | USER_SPARE_2 | R/W | 0h | (Default from NVM memory) |
| 0 | USER_SPARE_1 | R/W | 0h | (Default from NVM memory) |
ESM_MCU_START_REG is shown in Figure 8-199 and described in Table 8-159.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ESM_MCU_START | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-1 | RESERVED | R/W | 0h | |
| 0 | ESM_MCU_START | R/W | 0h | Control bit to start the ESM_MCU:
0h = ESM_MCU not started. Device clears ENABLE_DRV bit when bit ESM_MCU_EN=1 1h = ESM_MCU started. |
ESM_MCU_DELAY1_REG is shown in Figure 8-200 and described in Table 8-160.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_MCU_DELAY1 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ESM_MCU_DELAY1 | R/W | 0h | These bits configure the duration of the ESM_MCU delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. |
ESM_MCU_DELAY2_REG is shown in Figure 8-201 and described in Table 8-161.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_MCU_DELAY2 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ESM_MCU_DELAY2 | R/W | 0h | These bits configure the duration of the ESM_MCU delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. |
ESM_MCU_MODE_CFG is shown in Figure 8-202 and described in Table 8-162.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_MCU_MODE | ESM_MCU_EN | ESM_MCU_ENDRV | RESERVED | ESM_MCU_ERR_CNT_TH | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | ESM_MCU_MODE | R/W | 0h | This bit selects the mode for the ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = Level Mode 1h = PWM Mode |
| 6 | ESM_MCU_EN | R/W | 0h | ESM_MCU enable configuration bit: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_MCU_START=1, and - (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and - ESM_MCU_RST_INT=0, and - all other interrupt bits are cleared |
| 5 | ESM_MCU_ENDRV | R/W | 0h | Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1 |
| 4 | RESERVED | R/W | 0h | |
| 3-0 | ESM_MCU_ERR_CNT_TH | R/W | 0h | Configuration bits for the threshold of the ESM_MCU error-counter. The ESM_MCU starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_MCU_ERR_CNT[4:0] > ESM_MCU_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_MCU_START=0. |
ESM_MCU_HMAX_REG is shown in Figure 8-203 and described in Table 8-163.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_MCU_HMAX | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ESM_MCU_HMAX | R/W | 0h | These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. |
ESM_MCU_HMIN_REG is shown in Figure 8-204 and described in Table 8-164.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_MCU_HMIN | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ESM_MCU_HMIN | R/W | 0h | These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. |
ESM_MCU_LMAX_REG is shown in Figure 8-205 and described in Table 8-165.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_MCU_LMAX | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ESM_MCU_LMAX | R/W | 0h | These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. |
ESM_MCU_LMIN_REG is shown in Figure 8-206 and described in Table 8-166.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_MCU_LMIN | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ESM_MCU_LMIN | R/W | 0h | These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. |
ESM_MCU_ERR_CNT_REG is shown in Figure 8-207 and described in Table 8-167.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ESM_MCU_ERR_CNT | ||||||
| R-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | RESERVED | R | 0h | |
| 4-0 | ESM_MCU_ERR_CNT | R | 0h | Status bits to indicate the value of the ESM_MCU Error-Counter. The device clears these bits when ESM_MCU_START bit is 0, or when the device resets the MCU. |
ESM_SOC_START_REG is shown in Figure 8-208 and described in Table 8-168.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ESM_SOC_START | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-1 | RESERVED | R/W | 0h | |
| 0 | ESM_SOC_START | R/W | 0h | Control bit to start the ESM_SoC:
0h = ESM_SoC not started. Device clears ENABLE_DRV bit when bit ESM_SOC_EN=1 1h = ESM_SoC started |
ESM_SOC_DELAY1_REG is shown in Figure 8-209 and described in Table 8-169.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_SOC_DELAY1 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ESM_SOC_DELAY1 | R/W | 0h | These bits configure the duration of the ESM_SoC delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. |
ESM_SOC_DELAY2_REG is shown in Figure 8-210 and described in Table 8-170.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_SOC_DELAY2 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ESM_SOC_DELAY2 | R/W | 0h | These bits configure the duration of the ESM_SoC delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. |
ESM_SOC_MODE_CFG is shown in Figure 8-211 and described in Table 8-171.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_SOC_MODE | ESM_SOC_EN | ESM_SOC_ENDRV | RESERVED | ESM_SOC_ERR_CNT_TH | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | ESM_SOC_MODE | R/W | 0h | This bit selects the mode for the ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0. 0h = Level Mode 1h = PWM Mode |
| 6 | ESM_SOC_EN | R/W | 0h | ESM_SoC enable configuration bit: These bits can be only be written when control bit ESM_SOC_START=0. 0h = ESM_SoC disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_SoC enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_SOC_START=1, and - (ESM_SOC_FAIL_INT=0 or ESM_SOC_ENDRV=0), and - ESM_SOC_RST_INT=0, and - all other interrupt bits are cleared. |
| 5 | ESM_SOC_ENDRV | R/W | 0h | Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0 0h = ENABLE_DRV not cleared when ESM_SOC_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_SOC_FAIL_INT=1. |
| 4 | RESERVED | R/W | 0h | |
| 3-0 | ESM_SOC_ERR_CNT_TH | R/W | 0h | Configuration bits for the threshold of the ESM_SoC error-counter The ESM_SoC starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_SOC_ERR_CNT[4:0] > ESM_SOC_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_SOC_START=0. |
ESM_SOC_HMAX_REG is shown in Figure 8-212 and described in Table 8-172.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_SOC_HMAX | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ESM_SOC_HMAX | R/W | 0h | These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. |
ESM_SOC_HMIN_REG is shown in Figure 8-213 and described in Table 8-173.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_SOC_HMIN | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ESM_SOC_HMIN | R/W | 0h | These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. |
ESM_SOC_LMAX_REG is shown in Figure 8-214 and described in Table 8-174.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_SOC_LMAX | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ESM_SOC_LMAX | R/W | 0h | These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. |
ESM_SOC_LMIN_REG is shown in Figure 8-215 and described in Table 8-175.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESM_SOC_LMIN | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | ESM_SOC_LMIN | R/W | 0h | These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. |
ESM_SOC_ERR_CNT_REG is shown in Figure 8-216 and described in Table 8-176.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ESM_SOC_ERR_CNT | ||||||
| R-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | RESERVED | R | 0h | |
| 4-0 | ESM_SOC_ERR_CNT | R | 0h | Status bits to indicate the value of the ESM_SoC Error-Counter. The device clears these bits when ESM_SOC_START bit is 0, or when the device resets the SoC. |
REGISTER_LOCK is shown in Figure 8-217 and described in Table 8-177.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | REGISTER_LOCK_STATUS | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-1 | RESERVED | R/W | 0h | |
| 0 | REGISTER_LOCK_STATUS | R/W | 0h | Unlocking registers: write 0x9B to this address. Locking registers: write anything else than 0x9B to this address. Written 8 bit data to this address is not stored, only lock status can be read. REGISTER_LOCK_STATUS bit shows the lock status: 0h = Registers are unlocked 1h = Registers are locked |
MANUFACTURING_VER is shown in Figure 8-218 and described in Table 8-178.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SILICON_REV | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | SILICON_REV | R | 0h | SILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR SILICON_REV[2:0] - Metal |
CUSTOMER_NVM_ID_REG is shown in Figure 8-219 and described in Table 8-179.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CUSTOMER_NVM_ID | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | CUSTOMER_NVM_ID | R/W | 0h | Customer defined value if customer programmed part Same value as in TI_NVM_ID register if TI programmed part |
SOFT_REBOOT_REG is shown in Figure 8-220 and described in Table 8-180.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SOFT_REBOOT | ||||||
| R/W-0h | R/WSelfClrF-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-1 | RESERVED | R/W | 0h | |
| 0 | SOFT_REBOOT | R/WSelfClrF | 0h | Write 1 to request a soft reboot. This bit is automatically cleared. |
RTC_SECONDS is shown in Figure 8-221 and described in Table 8-181.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SECOND_1 | SECOND_0 | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0h | |
| 6-4 | SECOND_1 | R/W | 0h | Second digit of seconds (range is 0 up to 5) |
| 3-0 | SECOND_0 | R/W | 0h | First digit of seconds (range is 0 up to 9) |
RTC_MINUTES is shown in Figure 8-222 and described in Table 8-182.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MINUTE_1 | MINUTE_0 | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0h | |
| 6-4 | MINUTE_1 | R/W | 0h | Second digit of minutes (range is 0 up to 5) |
| 3-0 | MINUTE_0 | R/W | 0h | First digit of minutes (range is 0 up to 9) |
RTC_HOURS is shown in Figure 8-223 and described in Table 8-183.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PM_NAM | RESERVED | HOUR_1 | HOUR_0 | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | PM_NAM | R/W | 0h | Only used in PM_AM mode (otherwise it is set to 0)
0h = AM 1h = PM |
| 6 | RESERVED | R/W | 0h | |
| 5-4 | HOUR_1 | R/W | 0h | Second digit of hours(range is 0 up to 2) |
| 3-0 | HOUR_0 | R/W | 0h | First digit of hours (range is 0 up to 9) |
RTC_DAYS is shown in Figure 8-224 and described in Table 8-184.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DAY_1 | DAY_0 | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-4 | DAY_1 | R/W | 0h | Second digit of days (range is 0 up to 3) |
| 3-0 | DAY_0 | R/W | 0h | First digit of days (range is 0 up to 9) |
RTC_MONTHS is shown in Figure 8-225 and described in Table 8-185.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MONTH_1 | MONTH_0 | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | RESERVED | R/W | 0h | |
| 4 | MONTH_1 | R/W | 0h | Second digit of months (range is 0 up to 1) |
| 3-0 | MONTH_0 | R/W | 0h | First digit of months (range is 0 up to 9) |
RTC_YEARS is shown in Figure 8-226 and described in Table 8-186.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| YEAR_1 | YEAR_0 | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | YEAR_1 | R/W | 0h | Second digit of years (range is 0 up to 9) |
| 3-0 | YEAR_0 | R/W | 0h | First digit of years (range is 0 up to 9) |
RTC_WEEKS is shown in Figure 8-227 and described in Table 8-187.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | WEEK | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-3 | RESERVED | R/W | 0h | |
| 2-0 | WEEK | R/W | 0h | First digit of day of the week (range is 0 up to 6) |
ALARM_SECONDS is shown in Figure 8-228 and described in Table 8-188.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ALR_SECOND_1 | ALR_SECOND_0 | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0h | |
| 6-4 | ALR_SECOND_1 | R/W | 0h | Second digit of alarm programmation for seconds (range is 0 up to 5) |
| 3-0 | ALR_SECOND_0 | R/W | 0h | First digit of alarm programmation for seconds (range is 0 up to 9) |
ALARM_MINUTES is shown in Figure 8-229 and described in Table 8-189.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ALR_MINUTE_1 | ALR_MINUTE_0 | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0h | |
| 6-4 | ALR_MINUTE_1 | R/W | 0h | Second digit of alarm programmation for minutes (range is 0 up to 5) |
| 3-0 | ALR_MINUTE_0 | R/W | 0h | First digit of alarm programmation for minutes (range is 0 up to 9) |
ALARM_HOURS is shown in Figure 8-230 and described in Table 8-190.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ALR_PM_NAM | RESERVED | ALR_HOUR_1 | ALR_HOUR_0 | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | ALR_PM_NAM | R/W | 0h | Only used in PM_AM mode for alarm programmation (otherwise it is set to 0)
0h = AM 1h = PM |
| 6 | RESERVED | R/W | 0h | |
| 5-4 | ALR_HOUR_1 | R/W | 0h | Second digit of alarm programmation for hours(range is 0 up to 2) |
| 3-0 | ALR_HOUR_0 | R/W | 0h | First digit of alarm programmation for hours (range is 0 up to 9) |
ALARM_DAYS is shown in Figure 8-231 and described in Table 8-191.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ALR_DAY_1 | ALR_DAY_0 | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | |
| 5-4 | ALR_DAY_1 | R/W | 0h | Second digit of alarm programmation for days (range is 0 up to 3) |
| 3-0 | ALR_DAY_0 | R/W | 0h | First digit of alarm programmation for days (range is 0 up to 9) |
ALARM_MONTHS is shown in Figure 8-232 and described in Table 8-192.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ALR_MONTH_1 | ALR_MONTH_0 | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | RESERVED | R/W | 0h | |
| 4 | ALR_MONTH_1 | R/W | 0h | Second digit of alarm programmation for months (range is 0 up to 1) |
| 3-0 | ALR_MONTH_0 | R/W | 0h | First digit of alarm programmation for months (range is 0 up to 9) |
ALARM_YEARS is shown in Figure 8-233 and described in Table 8-193.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ALR_YEAR_1 | ALR_YEAR_0 | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | ALR_YEAR_1 | R/W | 0h | Second digit of alarm programmation for years (range is 0 up to 9) |
| 3-0 | ALR_YEAR_0 | R/W | 0h | First digit of alarm programmation for years (range is 0 up to 9) |
RTC_CTRL_1 is shown in Figure 8-234 and described in Table 8-194.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RTC_V_OPT | GET_TIME | SET_32_COUNTER | RESERVED | MODE_12_24 | AUTO_COMP | ROUND_30S | STOP_RTC |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RTC_V_OPT | R/W | 0h | RTC date / time register selection:
0h = Read access directly to dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEAR, RTC_WEEKS) 1h = Read access to static shadowed registers: (see GET_TIME bit). |
| 6 | GET_TIME | R/W | 0h | When writing a 1 into this register, the content of the dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEARS_ and RTC_WEEKS) is transferred into static shadowed registers. Each update of the shadowed registers needs to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then rewrite it to 1) Note: Shadowed registers, linked to the GET_TIME feature, are a parallel set of calendar static registers, at the same I2C addresses as the dynamic registers. Note: The GET_TIME feature loads the RTC counter in the shadow registers and make the content of the shadow registers available and stable for reading. Note: The GET_TIME bit has to be set to 0 and again to 1 to get a new timing value. Note: If the time reading is done without GET_TIME, the read value comes directly from the RTC counter and software has to manage the counter change during the reading. Time reading remains always at the same address, with or without using the GET_TIME feature. |
| 5 | SET_32_COUNTER | R/W | 0h | Note: This bit must only be used when the RTC is frozen.
0h = No action 1h = Set the 32kHz counter with RTC_COMP_MSB_REG/RTC_COMP_LSB_REG value |
| 4 | RESERVED | R/W | 0h | |
| 3 | MODE_12_24 | R/W | 0h | Note: It is possible to switch between the two modes at any time without disturbed the RTC, read or write are always performed with the current mode.
0h = 24 hours mode 1h = 12 hours mode (PM-AM mode) |
| 2 | AUTO_COMP | R/W | 0h | AUTO_COMP
0h = No auto compensation 1h = Auto compensation enabled |
| 1 | ROUND_30S | R/W | 0h | Note: This bit is a toggle bit, the micro-controller can only write one and RTC clears it. If the micro-controller sets the ROUND_30S bit and then read it, the micro-controller reads one until the rounding to the closest minute is performed at the next second. 0h = No update 1h = When a one is written, the time is rounded to the closest minute |
| 0 | STOP_RTC | R/W | 0h | STOP_RTC
0h = RTC is frozen 1h = RTC is running |
RTC_CTRL_2 is shown in Figure 8-235 and described in Table 8-195.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FIRST_STARTUP_DONE | STARTUP_DEST | FAST_BIST | LP_STANDBY_SEL | XTAL_SEL | XTAL_EN | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | FIRST_STARTUP_DONE | R/W | 0h | This bit controls if pre-configured NVM defaults are loaded to RTC domain reg bits during NVM read
0h = pre-configured NVM defaults are loaded to RTC domain bits 1h = pre-configured NVM defaults are not loaded to RTC domain bits |
| 6-5 | STARTUP_DEST | R/W | 0h | FSM start-up destination select. (Default from NVM memory) 0h = STANDBY/LP_STANDBY based on LP_STANDBY_SEL 1h = Reserved 2h = MCU_ONLY 3h = ACTIVE |
| 4 | FAST_BIST | R/W | 0h | FAST_BIST (Default from NVM memory) 0h = Logic and analog BIST is run at BOOT BIST. 1h = Only analog BIST is run at BOOT BIST. |
| 3 | LP_STANDBY_SEL | R/W | 0h | Control to enter low power standby state: (Default from NVM memory) 0h = LDOINT is enabled in standby state. 1h = Low power standby state is used as standby state (LDOINT is disabled). |
| 2-1 | XTAL_SEL | R/W | 0h | Crystal oscillator type select (Default from NVM memory) 0h = 6 pF 1h = 9 pF 2h = 12.5 pF 3h = Reserved |
| 0 | XTAL_EN | R/W | 0h | Crystal oscillator enable. (Default from NVM memory) 0h = Crystal oscillator is disabled 1h = Crystal oscillator is enabled |
RTC_STATUS is shown in Figure 8-236 and described in Table 8-196.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| POWER_UP | ALARM | TIMER | RESERVED | RUN | RESERVED | ||
| R/W1C-1h | R/W1C-0h | R/W1C-0h | R/W-0h | R-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | POWER_UP | R/W1C | 1h | Indicates that a reset occurred (bit cleared to 0 by writing 1) and that RTC data are not valid anymore. Note: POWER_UP is set by a reset, is cleared by writing one in this bit. Note: The POWER_UP (RTC_STATUS) and RESET_STATUS (RTC_RESET_STATUS) register bits indicate the same information. |
| 6 | ALARM | R/W1C | 0h | Indicates that an alarm interrupt has been generated (bit clear by writing 1). |
| 5 | TIMER | R/W1C | 0h | Indicates that an timer interrupt has been generated (bit clear by writing 1). |
| 4-2 | RESERVED | R/W | 0h | |
| 1 | RUN | R | 0h | Note: This bit shows the real state of the RTC, indeed because of STOP_RTC (RTC_CTRL) signal was resynchronized on 32kHz clock, the action of this bit is delayed.
0h = RTC is frozen 1h = RTC is running |
| 0 | RESERVED | R/W | 0h |
RTC_INTERRUPTS is shown in Figure 8-237 and described in Table 8-197.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | IT_ALARM | IT_TIMER | EVERY | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R/W | 0h | |
| 3 | IT_ALARM | R/W | 0h | Enable one interrupt when the alarm value is reached (TC ALARM registers: ALARM_SECONDS, ALARM_MINUTES, ALARM_HOURS, ALARM_DAYS, ALARM_MONTHS, ALARM_YEARS) by the TC registers NOTE: To prevent mis-firing of the ALARM interrupt, set the IT_ALARM = 0 prior to configuring the ALARM registers 0h = interrupt disabled 1h = interrupt enabled |
| 2 | IT_TIMER | R/W | 0h | Enable periodic interrupt NOTE: To prevent mis-firing of the TIMER interrupt, set the IT_TIMER = 0 prior to configuring the periodic time value 0h = interrupt disabled 1h = interrupt enabled |
| 1-0 | EVERY | R/W | 0h | Interrupt period
0h = every second 1h = every minute 2h = every hour 3h = every day |
RTC_COMP_LSB is shown in Figure 8-238 and described in Table 8-198.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COMP_LSB_RTC | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | COMP_LSB_RTC | R/W | 0h | This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [LSB] |
RTC_COMP_MSB is shown in Figure 8-239 and described in Table 8-199.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COMP_MSB_RTC | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | COMP_MSB_RTC | R/W | 0h | This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [MSB] |
RTC_RESET_STATUS is shown in Figure 8-240 and described in Table 8-200.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESET_STATUS_RTC | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-1 | RESERVED | R/W | 0h | |
| 0 | RESET_STATUS_RTC | R/W | 0h | This bit can only be set to one and is cleared when a manual reset or a POR (case of VOUT_LDO_RTC below the LDO_RTC POR level) occur. If this bit is reset it means that the RTC has lost its configuration. Note: The RESET_STATUS (RTC_RESET_STATUS) and POWER_UP (RTC_STATUS) register bits indicate the same information. |
SCRATCH_PAD_REG_1 is shown in Figure 8-241 and described in Table 8-201.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SCRATCH_PAD_1 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | SCRATCH_PAD_1 | R/W | 0h | Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. |
SCRATCH_PAD_REG_2 is shown in Figure 8-242 and described in Table 8-202.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SCRATCH_PAD_2 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | SCRATCH_PAD_2 | R/W | 0h | Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. |
SCRATCH_PAD_REG_3 is shown in Figure 8-243 and described in Table 8-203.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SCRATCH_PAD_3 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | SCRATCH_PAD_3 | R/W | 0h | Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. |
SCRATCH_PAD_REG_4 is shown in Figure 8-244 and described in Table 8-204.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SCRATCH_PAD_4 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | SCRATCH_PAD_4 | R/W | 0h | Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. |
PFSM_DELAY_REG_1 is shown in Figure 8-245 and described in Table 8-205.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PFSM_DELAY1 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | PFSM_DELAY1 | R/W | 0h | Generic delay1 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) |
PFSM_DELAY_REG_2 is shown in Figure 8-246 and described in Table 8-206.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PFSM_DELAY2 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | PFSM_DELAY2 | R/W | 0h | Generic delay2 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) |
PFSM_DELAY_REG_3 is shown in Figure 8-247 and described in Table 8-207.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PFSM_DELAY3 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | PFSM_DELAY3 | R/W | 0h | Generic delay3 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) |
PFSM_DELAY_REG_4 is shown in Figure 8-248 and described in Table 8-208.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PFSM_DELAY4 | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | PFSM_DELAY4 | R/W | 0h | Generic delay4 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) |
WD_ANSWER_REG is shown in Figure 8-249 and described in Table 8-209.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WD_ANSWER | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | WD_ANSWER | R/W | 0h | MCU answer byte. The MCU must write the expected reference Answer-x into this register. Each watchdog question requires four answer bytes: - Three answer bytes (Answer-3, Answer-2, Answer-1) must be written in Window-1. - The fourth (final) answer-byte (Answer-0) must be written in Window-2. The number of written answer bytes is tracked with the WD_ANSW_CNT counter in the WD_QUESTION_ANSW_CNT register. These bits only apply for Watchdog in Q&A mode. |
WD_QUESTION_ANSW_CNT is shown in Figure 8-250 and described in Table 8-210.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | WD_ANSW_CNT | WD_QUESTION | |||||
| R-0h | R-3h | R-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R | 0h | |
| 5-4 | WD_ANSW_CNT | R | 3h | Current, received watchdog-answer count state. These bits only apply for Watchdog in Q&A mode. |
| 3-0 | WD_QUESTION | R | 0h | Watchdog question. The MCU must read (or calculate ) the current watchdog question value to generate correct answers. These bits only apply for Watchdog in Q&A mode. |
WD_WIN1_CFG is shown in Figure 8-251 and described in Table 8-211.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | WD_WIN1 | ||||||
| R/W-0h | R/W-7Fh | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0h | |
| 6-0 | WD_WIN1 | R/W | 7Fh | These bits are for programming the duration of Watchdog Window-1 (see Watchdoc chapter). These bits can be only be written when the watchdog is in the Long Window. |
WD_WIN2_CFG is shown in Figure 8-252 and described in Table 8-212.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | WD_WIN2 | ||||||
| R/W-0h | R/W-7Fh | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0h | |
| 6-0 | WD_WIN2 | R/W | 7Fh | These bits are for programming the duration of Watchdog Window-2 (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. |
WD_LONGWIN_CFG is shown in Figure 8-253 and described in Table 8-213.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WD_LONGWIN | |||||||
| R/W-FFh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | WD_LONGWIN | R/W | FFh | These bits are for programming the duration of Watchdog Long Window (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. (Default from NVM memory) |
WD_MODE_REG is shown in Figure 8-254 and described in Table 8-214.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | WD_PWRHOLD | WD_MODE_SELECT | WD_RETURN_LONGWIN | ||||
| R/W-0h | R/W-0h | R/W-1h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-3 | RESERVED | R/W | 0h | |
| 2 | WD_PWRHOLD | R/W | 0h | Device sets WD_PWRHOLD if hardware condition on pin DISABLE_WDOG (mapped to GPIO8 pin) is applied at start-up (see Watchdog chapter). MCU can write this bit to 1. MCU needs to clear this bit to get out of the Long Window: 0h = watchdog goes out of the Long Window and starts the first watchdog-sequence when the configured Long Window time-interval elapses 1h = watchdog stays in Long Window |
| 1 | WD_MODE_SELECT | R/W | 1h | Watchdog mode-select: MCU can set this to required value only when watchdog is in the Long Window. 0h = Trigger Mode 1h = Q&A mode. |
| 0 | WD_RETURN_LONGWIN | R/W | 0h | MCU can set this bit to put the watchdog from operating back to the Long Window (see Watchdog chapter):
0h = Watchdog continues operating 1h = Watchdog returns to Long-Window after completion of the current watchdog-sequence. |
WD_QA_CFG is shown in Figure 8-255 and described in Table 8-215.
Return to the Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WD_QA_FDBK | WD_QA_LFSR | WD_QUESTION_SEED | |||||
| R/W-0h | R/W-0h | R/W-Ah | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | WD_QA_FDBK | R/W | 0h | Feedback configuration bits for the watchdog question. These bits control the sequence of the generated questions and respective reference answers (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. |
| 5-4 | WD_QA_LFSR | R/W | 0h | LFSR-equation configuration bits for the watchdog question (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. |
| 3-0 | WD_QUESTION_SEED | R/W | Ah | The watchdog question-seed value (see Watchdog chapter). The MCU updates the question-seed value to generate a set of new questions. These bits can be only be written when the watchdog is in the Long Window. |
WD_ERR_STATUS is shown in Figure 8-256 and described in Table 8-216.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WD_RST_INT | WD_FAIL_INT | WD_ANSW_ERR | WD_SEQ_ERR | WD_ANSW_EARLY | WD_TRIG_EARLY | WD_TIMEOUT | WD_LONGWIN_TIMEOUT_INT |
| R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | WD_RST_INT | R/W1C | 0h | Latched status bit to indicate that the device went through warm reset due to WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). Write 1 to clear. |
| 6 | WD_FAIL_INT | R/W1C | 0h | Latched status bit to indicate that the watchdog has cleared the ENABLE_DRV bit due to WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. Write 1 to clear. |
| 5 | WD_ANSW_ERR | R/W1C | 0h | Latched status bit to indicate that the watchdog has detected an incorrect answer-byte. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. |
| 4 | WD_SEQ_ERR | R/W1C | 0h | Latched status bit to indicate that the watchdog has detected an incorrect sequence of the answer-bytes. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. |
| 3 | WD_ANSW_EARLY | R/W1C | 0h | Latched status bit to indicate that the watchdog has received the final answer-byte in Window-1. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. |
| 2 | WD_TRIG_EARLY | R/W1C | 0h | Latched status bit to indicate that the watchdog has received the watchdog-trigger in Window-1. Write 1 to clear. This bit only applies for Watchdog in Trigger mode. |
| 1 | WD_TIMEOUT | R/W1C | 0h | Latched status bit to indicate that the watchdog has detected a time-out event in the started watchdog sequence. Write 1 to clear. |
| 0 | WD_LONGWIN_TIMEOUT_INT | R/W1C | 0h | Latched status bit to indicate that device went through warm reset due to elapse of Long Window time-interval. Write 1 to clear interrupt. |
WD_THR_CFG is shown in Figure 8-257 and described in Table 8-217.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WD_RST_EN | WD_EN | WD_FAIL_TH | WD_RST_TH | ||||
| R/W-1h | R/W-1h | R/W-7h | R/W-7h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | WD_RST_EN | R/W | 1h | Watchdog reset configuration bit: This bit can be only be written when the watchdog is in the Long Window. 0h = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) 1h = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). |
| 6 | WD_EN | R/W | 1h | Watchdog enable configuration bit: This bit can be only be written when the watchdog is in the Long Window. (Default from NVM memory) 0h = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt status bits are cleared 1h = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if: - watchdog is out of the Long Window - WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0] - WD_FIRST_OK=1 - all other interrupt status bits are cleared. |
| 5-3 | WD_FAIL_TH | R/W | 7h | Configuration bits for the 1st threshold of the watchdog fail counter: Device clears ENABLE_DRV bit when WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. These bits can be only be written when the watchdog is in the Long Window. |
| 2-0 | WD_RST_TH | R/W | 7h | Configuration bits for the 2nd threshold of the watchdog fail counter: Device goes through warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). These bits can be only be written when the watchdog is in the Long Window. |
WD_FAIL_CNT_REG is shown in Figure 8-258 and described in Table 8-218.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | WD_BAD_EVENT | WD_FIRST_OK | RESERVED | WD_FAIL_CNT | |||
| R-0h | R-0h | R-1h | R-0h | R-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R | 0h | |
| 6 | WD_BAD_EVENT | R | 0h | Status bit to indicate that the watchdog has detected a bad event in the current watchdog sequence. The device clears this bit at the end of the watchdog sequence. |
| 5 | WD_FIRST_OK | R | 1h | Status bit to indicate that the watchdog has detected a good event. The device clears this bit when the watchdog goes to the Long Window. |
| 4 | RESERVED | R | 0h | |
| 3-0 | WD_FAIL_CNT | R | 0h | Status bits to indicate the value of the Watchdog Fail Counter. The device clears these bits when the watchdog goes to the Long Window. |