ZHCSKK3A December   2019  – April 2021 TPS6594-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. 功能图
  5. Revision History
  6. Description (continued)
  7. Pin Configuration and Functions
    1. 7.1 Digital Signal Descriptions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)
    6. 8.6  Low Noise Low Drop-Out Regulator (LDO4)
    7. 8.7  Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT)
    8. 8.8  BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators
    9. 8.9  Reference Generator (BandGap)
    10. 8.10 Monitoring Functions
    11. 8.11 Clocks, Oscillators, and PLL
    12. 8.12 Thermal Monitoring and Shutdown
    13. 8.13 System Control Thresholds
    14. 8.14 Current Consumption
    15. 8.15 Backup Battery Charger
    16. 8.16 Digital Input Signal Parameters
    17. 8.17 Digital Output Signal Parameters
    18. 8.18 I/O Pullup and Pulldown Resistance
    19. 8.19 I2C Interface
    20. 8.20 Serial Peripheral Interface (SPI)
  9. Typical Characteristics
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  System Supply Voltage Monitor and Over-Voltage Protection
      2. 10.3.2  Power Resources (Bucks and LDOs)
        1. 10.3.2.1 Buck Regulators
          1. 10.3.2.1.1 Overview
          2. 10.3.2.1.2 Multi-Phase Operation and Phase-Adding or Shedding
          3. 10.3.2.1.3 Transition Between PWM and PFM Modes
          4. 10.3.2.1.4 Multi-Phase Buck Regulator Configurations
          5. 10.3.2.1.5 Spread-Spectrum Mode
          6. 10.3.2.1.6 Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          7. 10.3.2.1.7 Buck Output Voltage Setting
        2. 10.3.2.2 Sync Clock Functionality
        3.      
        4. 10.3.2.3 Low Dropout Regulators (LDOs)
          1. 10.3.2.3.1 LDOVINT
          2. 10.3.2.3.2 LDOVRTC
          3. 10.3.2.3.3 LDO1, LDO2, and LDO3
          4. 10.3.2.3.4 Low-Noise LDO (LDO4)
      3. 10.3.3  Residual Voltage Checking
      4. 10.3.4  Output Voltage Monitor and PGOOD Generation
      5. 10.3.5  Thermal Monitoring
        1. 10.3.5.1 Thermal Warning Function
        2. 10.3.5.2 Thermal Shutdown
      6. 10.3.6  Backup Supply Power-Path
      7. 10.3.7  General-Purpose I/Os (GPIO Pins)
      8. 10.3.8  nINT, EN_DRV, and nRSTOUT Pins
      9. 10.3.9  Interrupts
      10. 10.3.10 RTC
        1. 10.3.10.1 General Description
        2. 10.3.10.2 Time Calendar Registers
          1. 10.3.10.2.1 TC Registers Read Access
          2. 10.3.10.2.2 TC Registers Write Access
        3. 10.3.10.3 RTC Alarm
        4. 10.3.10.4 RTC Interrupts
        5. 10.3.10.5 RTC 32-kHz Oscillator Drift Compensation
      11. 10.3.11 Watchdog (WD)
        1. 10.3.11.1 Watchdog Fail Counter and Status
        2. 10.3.11.2 Watchdog Start-Up and Configuration
        3. 10.3.11.3 MCU to Watchdog Synchronization
        4. 10.3.11.4 Watchdog Disable Function
        5. 10.3.11.5 Watchdog Sequence
        6. 10.3.11.6 Watchdog Trigger Mode
        7. 10.3.11.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8. 10.3.11.8 Watchdog Question-Answer Mode
          1. 10.3.11.8.1 Watchdog Q&A Related Definitions
          2. 10.3.11.8.2 Question Generation
          3. 10.3.11.8.3 Answer Comparison
            1. 10.3.11.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 10.3.11.8.3.2 Watchdog Sequence Events and Status Updates
            3. 10.3.11.8.3.3 Watchdog Q&A Sequence Scenarios
      12. 10.3.12 Error Signal Monitor (ESM)
        1. 10.3.12.1 ESM Error-Handling Procedure
          1. 10.3.12.1.1 Level Mode
          2. 10.3.12.1.2 PWM Mode
            1. 10.3.12.1.2.1 Good-Events and Bad-Events
            2. 10.3.12.1.2.2 ESM Error-Counter
            3. 10.3.12.1.2.3 ESM Start-Up in PWM Mode
            4. 10.3.12.1.2.4 ESM Flow Chart and Timing Diagrams in PWM Mode
    4. 10.4 Device Functional Modes
      1. 10.4.1 Device State Machine
        1. 10.4.1.1 Fixed Device Power FSM
          1. 10.4.1.1.1 Register Resets and EEPROM read at INIT state
        2. 10.4.1.2 Pre-Configurable Mission States
          1. 10.4.1.2.1 PFSM Commands
            1. 10.4.1.2.1.1  REG_WRITE_IMM Command
            2. 10.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 10.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 10.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 10.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 10.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 10.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 10.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 10.4.1.2.1.9  SREG_READ_REG Command
            10. 10.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 10.4.1.2.1.11 WAIT Command
            12. 10.4.1.2.1.12 DELAY_IMM Command
            13. 10.4.1.2.1.13 DELAY_SREG Command
            14. 10.4.1.2.1.14 TRIG_SET Command
            15. 10.4.1.2.1.15 TRIG_MASK Command
            16. 10.4.1.2.1.16 END Command
          2. 10.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 10.4.1.2.3 Mission State Configuration
          4. 10.4.1.2.4 Pre-Configured Hardware Transitions
            1. 10.4.1.2.4.1 ON Requests
            2. 10.4.1.2.4.2 OFF Requests
            3. 10.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 10.4.1.2.4.4 WKUP1 and WKUP2 Functions
            5. 10.4.1.2.4.5 LP_WKUP Pins for Waking Up from LP STANDBY
        3. 10.4.1.3 Error Handling Operations
          1. 10.4.1.3.1 Power Rail Output Error
          2. 10.4.1.3.2 Boot BIST Error
          3. 10.4.1.3.3 Runtime BIST Error
          4. 10.4.1.3.4 Catastrophic Error
          5. 10.4.1.3.5 Watchdog (WDOG) Error
          6. 10.4.1.3.6 Error Signal Monitor (ESM) Error
          7. 10.4.1.3.7 Warnings
        4. 10.4.1.4 Device Startup Timing
        5. 10.4.1.5 Power Sequences
        6. 10.4.1.6 First Supply Detection
        7. 10.4.1.7 Register Power Domains and Reset Levels
      2. 10.4.2 Multi-PMIC Synchronization
        1. 10.4.2.1 SPMI Interface System Setup
        2. 10.4.2.2 Transmission Protocol and CRC
        3. 10.4.2.3 SPMI Slave Communication to SPMI Master
          1. 10.4.2.3.1 Incomplete Communication from SPMI Slave to SPMI Master
        4. 10.4.2.4 SPMI BIST Overview
    5. 10.5 Control Interfaces
      1. 10.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 10.5.2 I2C-Compatible Interface
        1. 10.5.2.1 Data Validity
        2. 10.5.2.2 Start and Stop Conditions
        3. 10.5.2.3 Transferring Data
        4. 10.5.2.4 Auto-Increment Feature
      3. 10.5.3 Serial Peripheral Interface (SPI)
    6. 10.6 Configurable Registers
      1. 10.6.1 Register Page Partitioning
      2. 10.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 10.6.3 CRC Protection for User Registers
      4. 10.6.4 Register Write Protection
        1. 10.6.4.1 ESM and WDOG Configuration Registers
        2. 10.6.4.2 User Registers
    7. 10.7 Register Maps
      1. 10.7.1 TPS6594-Q1 Registers
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Powering a Processor
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
          1. 11.2.1.2.1 VCCA, VSYS_SENSE, and OVPGDRV
          2. 11.2.1.2.2 Internal LDOs
          3. 11.2.1.2.3 Crystal Oscillator
          4. 11.2.1.2.4 Buck Input Capacitors
          5. 11.2.1.2.5 Buck Output Capacitors
          6. 11.2.1.2.6 Buck Inductors
          7. 11.2.1.2.7 LDO Input Capacitors
          8. 11.2.1.2.8 LDO Output Capacitors
          9. 11.2.1.2.9 Digital Signal Connections
      2. 11.2.2 Application Curves
    3. 11.3 Power Supply Recommendations
    4. 11.4 Layout
      1. 11.4.1 Layout Guidelines
      2. 11.4.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 第三方产品免责声明
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
    3. 12.3 Documentation Support
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 支持资源
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

特性

  • 符合汽车应用标准
  • 具有符合 AEC-Q100 的下列结果:
    • 器件的输入电源电压范围为 3V 至 5.5V
    • 器件温度 1 级:–40°C 至 +125℃ 环境温度范围
    • 器件 HBM 分类等级 2
    • 器件 CDM 分类等级 C4A
  • SafeTI 半导体元件
    • 专为功能安全应用而设计
    • 可帮助使 ISO 26262 系统设计符合 ASIL D 的文档
    • 可满足 ASIL D 要求的系统功能和硬件完整性
    • 输入电源监控和过压保护
    • 窗口式电压和过流监控器
    • 集成式 Q&A 或触发模式看门狗模块
    • 双通道或 PWM 错误信号监控 (ESM) 支持具有集成式安全 MCU 的处理器
    • 具有高温报警和热关断功能的温度监控
    • 带有运行或保持上电序列以及复位释放选项的 NVM 位完整性错误检测
  • 低功耗
    • 2μA 典型关断电流
    • 仅备用电源模式下的典型值为 7μA
    • 低功耗待机模式下的典型值为 20μA
  • 五个开关模式电源降压稳压器:
    • 输出电压范围:0.3V 至 3.34V(电压阶跃为 5mV、10mV 或 20mV)
    • 一个为 4A,三个为 3.5A,一个为 2A
    • 四个具有灵活多相位功能的降压稳压器,单轨的拉电流高达 14A
    • 具有短路和过流保护
    • 内部软启动可限制浪涌电流
    • 开关频率为 2.2MHz/4.4MHz
    • 可与外部时钟输入同步
  • 三个具有可配置旁路模式的低压降 (LDO) 线性稳压器
    • 线性稳压模式下的输出电压范围:0.6V 至 3.3V(电压阶跃为 50mV)
    • 旁路模式下的输出电压范围:1.7V 至 3.3V
    • 500mA 电流,具有短路和过流保护
  • 一个具有低噪声的低压降 (LDO) 线性稳压器
    • 输出电压范围:1.2V 至 3.3V(电压阶跃为 25mV)
    • 300mA 电流,具有短路和过流保护
  • 电源序列控制:
    • 电源状态之间的上电和断电序列可配置 (NVM)
    • 数字输出信号可添加至电源序列
    • 数字输入信号可用于触发电源序列转换
  • 32kHz 晶体振荡器,可输出缓冲式 32kHz 时钟输出
  • 具有警报和定期唤醒机制的实时时钟 (RTC)
  • 具有一个 SPI 或两个 I2C 控制接口,且第二个 I2C 接口专用于 Q&A 看门狗通信
  • 封装选项:
    • 8mm × 8mm 56 引脚 VQFNP,间距为 0.5mm