ZHCSJK5C January   2018  – October 2020 TCAN4550-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specification
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings, IEC ESD and ISO Transient Specification
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Supply Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VSUP Pin
      2. 8.3.2  VIO Pin
      3. 8.3.3  VCCOUT Pin
      4. 8.3.4  GND
      5. 8.3.5  INH Pin
      6. 8.3.6  WAKE Pin
      7. 8.3.7  FLTR Pin
      8. 8.3.8  RST Pin
      9. 8.3.9  OSC1 and OSC2 Pins
      10. 8.3.10 nWKRQ Pin
      11. 8.3.11 nINT Interrupt Pin
      12. 8.3.12 GPIO1 Pin
      13. 8.3.13 GPO2 Pin
      14. 8.3.14 CANH and CANL Bus Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Sleep Mode
        1. 8.4.3.1 Bus Wake via RXD_INT Request (BWRR) in Sleep Mode
        2. 8.4.3.2 Local Wake Up (LWU) via WAKE Input Terminal
      4. 8.4.4 Test Mode
      5. 8.4.5 Failsafe Feature
      6. 8.4.6 Protection Features
        1. 8.4.6.1 Watchdog Function
        2. 8.4.6.2 Driver and Receiver Function
        3. 8.4.6.3 Floating Terminals
        4. 8.4.6.4 TXD_INT Dominant Timeout (DTO)
        5. 8.4.6.5 CAN Bus Short Circuit Current Limiting
        6. 8.4.6.6 Thermal Shutdown
        7. 8.4.6.7 Under Voltage Lockout (UVLO) and Unpowered Device
          1. 8.4.6.7.1 UVSUP and UVCCOUT
          2. 8.4.6.7.2 UVIO
          3. 8.4.6.7.3 Fault and M_CAN Core Behavior:
      7. 8.4.7 CAN FD
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 Chip Select Not (nCS):
        2. 8.5.1.2 SPI Clock Input (SCLK):
        3. 8.5.1.3 SPI Data Input (SDI):
        4. 8.5.1.4 SPI Data Output (SDO):
      2. 8.5.2 Register Descriptions
      3.     
    6. 8.6 Register Maps
      1. 8.6.1 Device ID and Interrupt/Diagnostic Flag Registers: 16'h0000 to 16'h002F
        1. 8.6.1.1 DEVICE_ID1[31:0] (address = h0000) [reset = h4E414354]
        2. 8.6.1.2 DEVICE_ID2[31:0] (address = h0004) [reset = h30353534]
        3. 8.6.1.3 Revision (address = h0008) [reset = h00110201]
        4. 8.6.1.4 Status (address = h000C) [reset = h0000000U]
      2. 8.6.2 Device Configuration Registers: 16'h0800 to 16'h08FF
        1. 8.6.2.1 Modes of Operation and Pin Configuration Registers (address = h0800) [reset = hC8000468]
        2. 8.6.2.2 Timestamp Prescalar (address = h0804) [reset = h00000002]
        3. 8.6.2.3 Test Register and Scratch Pad (address = h0808) [reset = h00000000]
        4. 8.6.2.4 Test Register (address = h080C) [reset = h00000000]
      3. 8.6.3 Interrupt/Diagnostic Flag and Enable Flag Registers: 16'h0820/0824 and 16'h0830
        1. 8.6.3.1 Interrupts (address = h0820) [reset = h00100000]
        2. 8.6.3.2 MCAN Interrupts (address = h0824) [reset = h00000000]
        3. 8.6.3.3 Interrupt Enables (address = h0830 ) [reset = hFFFFFFFF]
      4. 8.6.4 CAN FD Register Set: 16'h1000 to 16'h10FF
        1. 8.6.4.1  Core Release Register (address = h1000) [reset = hrrrddddd]
        2. 8.6.4.2  Endian Register (address = h1004) [reset = h87654321]
        3. 8.6.4.3  Customer Register (address = h1008) [reset = h00000000]
        4. 8.6.4.4  Data Bit Timing & Prescaler (address = h100C) [reset = h0000A33]
        5. 8.6.4.5  Test Register (address = h1010 ) [reset = h00000000]
        6. 8.6.4.6  RAM Watchdog (address = h1014) [reset = h00000000]
        7. 8.6.4.7  Control Register (address = h1018) [reset = 0000 0019]
        8. 8.6.4.8  Nominal Bit Timing & Prescaler Register (address = h101C) [reset = h06000A03]
        9. 8.6.4.9  Timestamp Counter Configuration (address = h1020) [reset = h00000000]
        10. 8.6.4.10 Timestamp Counter Value (address = h1024) [reset = h00000000]
        11. 8.6.4.11 Timeout Counter Configuration (address = h1028) [reset = hFFFF0000]
        12. 8.6.4.12 Timeout Counter Value (address = h102C) [reset = h0000FFFF]
        13. 8.6.4.13 Reserved (address = h1030 - h103C) [reset = h00000000]
        14. 8.6.4.14 Error Counter Register (address = h1040) [reset = h00000000]
        15. 8.6.4.15 Protocol Status Register (address = h1044) [reset = h00000707]
        16. 8.6.4.16 Transmitter Delay Compensation Register (address = h1048) [reset = h00000000]
        17. 8.6.4.17 Reserved (address = h104C) [reset = h00000000]
        18. 8.6.4.18 Interrupt Register (address = h1050) [reset = h00000000]
        19. 8.6.4.19 Interrupt Enable (address = h1054) [reset = h00000000]
        20. 8.6.4.20 Interrupt Line Select (address = h1058) [reset = h00000000]
        21. 8.6.4.21 Interrupt Line Enable (address = h105C) [reset = h00000000]
        22. 8.6.4.22 Reserved (address = h1060 - h107C) [reset = h00000000]
        23. 8.6.4.23 Global Filter Configuration (address = h1080) [reset = h00000000]
        24. 8.6.4.24 Standard ID Filter Configuration (address = h1084) [reset = h00000000]
        25. 8.6.4.25 Extended ID Filter Configuration (address = h1088) [reset = h00000000]
        26. 8.6.4.26 Reserved (address = h108C) [reset = h00000000]
        27. 8.6.4.27 Extended ID AND Mask (address = h1090) [reset = h1FFFFFFF]
        28. 8.6.4.28 High Priority Message Status (address = h1094) [reset = h00000000]
        29. 8.6.4.29 New Data 1 (address = h1098) [reset = h00000000]
        30. 8.6.4.30 New Data 2 (address = h109C) [reset = h00000000]
        31. 8.6.4.31 Rx FIFO 0 Configuration (address = h10A0) [reset = h00000000]
        32. 8.6.4.32 Rx FIFO 0 Status (address = h10A4) [reset = h00000000]
        33. 8.6.4.33 Rx FIFO 0 Acknowledge (address = h10A8) [reset = h00000000]
        34. 8.6.4.34 Rx Buffer Configuration (address = h10AC) [reset = h00000000]
        35. 8.6.4.35 Rx FIFO 1 Configuration (address = h10B0) [reset = h00000000]
        36. 8.6.4.36 Rx FIFO 1 Status (address = h10B4) [reset = h00000000]
        37. 8.6.4.37 Rx FIFO 1 Acknowledge (address = h10B8) [reset = h00000000]
        38. 8.6.4.38 Rx Buffer/FIFO Element Size Configuration (address = h10BC) [reset = h00000000]
        39. 8.6.4.39 Tx Buffer Configuration (address = h10C0) [reset = h00000000]
        40. 8.6.4.40 Tx FIFO/Queue Status (address = h10C4) [reset = h00000000]
        41. 8.6.4.41 Tx Buffer Element Size Configuration (address = h10C8) [reset = h00000000]
        42. 8.6.4.42 Tx Buffer Request Pending (address = h10CC) [reset = h00000000]
        43. 8.6.4.43 Tx Buffer Add Request (address = h10D0) [reset = h00000000]
          1. 8.6.4.43.1  Tx Buffer Cancellation Request (address = h10D4 [reset = h00000000]
          2. 8.6.4.43.2  Tx Buffer Add Request Transmission Occurred (address = h10D8) [reset = h00000000]
          3. 8.6.4.43.3  Tx Buffer Cancellation Finished (address = h10DC) [reset = h00000000]
          4. 8.6.4.43.4  Tx Buffer Transmission Interrupt Enable (address = h10E0) [reset = h00000000]
          5. 8.6.4.43.5  Tx Buffer Cancellation Finished Interrupt Enable (address = h10E4) [reset = h00000000]
          6. 8.6.4.43.6  Reserved (address = h10E8) [reset = h00000000]
          7. 8.6.4.43.7  Reserved (address = h10EC) [reset = h00000000]
          8. 8.6.4.43.8  Tx Event FIFO Configuration (address = h10F0) [reset = h00000000]
          9. 8.6.4.43.9  Tx Event FIFO Status (address = h10F4) [reset = h00000000]
          10. 8.6.4.43.10 Tx Event FIFO Acknowledge (address = h10F8) [reset = h00000000]
          11. 8.6.4.43.11 Reserved (address = h10FC) [reset = h00000000]
  9. Application and Implementation
    1. 9.1 Application Design Consideration
      1. 9.1.1 Crystal and Clock Input Requirements
      2. 9.1.2 Bus Loading, Length and Number of Nodes
      3. 9.1.3 CAN Termination
        1. 9.1.3.1 Termination
        2.      
        3. 9.1.3.2 CAN Bus Biasing
      4. 9.1.4 INH Brownout Behavior
    2. 9.2 Typical Application
      1. 9.2.1 Detailed Requirements
      2. 9.2.2 Detailed Design Procedures
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
        1. 12.1.1.1 CAN Transceiver Physical Layer Standards:
        2. 12.1.1.2 EMC requirements:
        3. 12.1.1.3 Conformance Test requirements:
        4. 12.1.1.4 Support Documents
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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Electrical Characteristics

over operating free-air temperature range for – 40 ℃ ≤ TA ≤ 125 ℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
CAN DRIVER ELECTRICAL CHARACTERISTICS
VO(D) Bus output voltage (dominant) CANH See Figure 7-3 and Figure 7-4, TXD_INT = 0 V, EN = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open 2.75 4.5 V
Bus output voltage (dominant) CANL 0.5 2.25 V
VO(R) Bus output voltage (recessive) See Figure 7-1 and Figure 7-4, TXD_INT = VIO, RL = open (no load), RCM = open 2 2.5 3 V
V(DIFF) Maximum differential voltage rating See Figure 7-1 and Figure 7-4 –5.0 10 V
VO(STB) Bus output voltage (Standby Mode) CANH See Figure 7-1 and Figure 7-4, TXD_INT = VIO, RL = open (no load), RCM = open –0.1 0.1 V
Bus output voltage (Standby Mode) CANL –0.1 0.1 V
Bus output voltage (Standby Mode) CANH - CANL –0.2 0.2 V
VOD(D) Differential output voltage (dominant) See Figure 7-1 and Figure 7-4, TXD_INT = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open 1.5 3 V
See Figure 7-1 and Figure 7-4, TXD_INT = 0 V, 45 Ω ≤ RL ≤ 70 Ω, CL = open, RCM = open 1.4 3 V
See Figure 7-1 and Figure 7-4, TXD_INT = 0 V, RL = 2.24 kΩ, CL = open, RCM = open 1.5 5 V
VOD(R) Differential output voltage (recessive) See Figure 7-1 and Figure 7-4, TXD_INT = VIO, RL = 60 Ω, CL = open, RCM = open –120 12 mV
See Figure 7-1 and Figure 7-4, TXD_INT = VIO, RL = open (no load), CL = open, RCM = open –50 50 mV
VSYM Output symmetry (dominant or recessive)
( VO(CANH) + VO(CANL)) / VCC
See Figure 7-1 and Figure 7-4, RL = 60 Ω, CL = open, RCM = open, C1 = 4.7 nF, TXD_INT - 250 kHZ, 1 MHz 0.9 1.1 V/V
VSYM_DC Output symmetry (dominant or recessive) (VCC – VO(CANH) – VO(CANL)) with a frequency that corresponds to the highest bit rate for which the HS-PMA implementation is intended, however, at most 1 MHz (2 Mbit/s) See Figure 7-1 and Figure 7-4, RL = 60 Ω, CL = open, RCM = open, C1 = 4.7 nF –300 300 mV
IOS_DOM Short-circuit steady-state output current, dominant See Figure 7-1 and Figure 7-8, -3.0 V ≤ VCANH ≤ 18.0 V, CANL = open, TXD_INT = 0 V –100 mA
See Figure 7-1 and Figure 7-8, -3.0 V ≤ VCANL ≤+18.0 V, CANH = open, TXD_INT = 0 V 100 mA
IOS_REC Short-circuit steady-state output current, recessive See Figure 7-1 and Figure 7-8, – 27 V ≤ VBUS ≤ 32 V, VBUS = CANH = CANL –5 5 mA
CAN RECEIVER ELECTRICAL CHARACTERISTICS
VITdom Receiver dominant state differential input voltage range, bus biasing active -12.0 V ≤ VCANL ≤ +12.0 V
-12.0 V ≤ VCANH ≤ +12.0 V  See Figure 7-5Table 8-3
0.9 8 V
VITrec Receiver recessive state differential input voltage range bus biasing active –3.0 0.5 V
VHYS Hysteresis voltage for input-threshold, normal modes See Figure 7-5, Table 8-3 120 mV
VIT(ENdom) Receiver dominant state differential input voltage range, bus biasing inactive (VDiff) -12.0 V ≤ VCANL ≤ +12.0 V
-12.0 V ≤ VCANH ≤ +12.0 V See Figure 7-5Table 8-3
1.15 8 V
VIT(ENrec) Receiver recessive state differential input voltage range, bus biasing inactive (VDiff) -12.0 V ≤ VCANL ≤ +12.0 V
-12.0 V ≤ VCANH ≤ +12.0 V See Figure 7-5Table 8-3
–3 0.4 V
VCM Common mode range: normal See Figure 7-5, Table 8-3 –12 12 V
VCM(EN) Common mode range: standby mode See Figure 7-5, Table 8-3 –12 12 V
IIOFF(LKG) Power-off (unpowered) bus input leakage current VCANH = VCANL = 5 V, Vsup to GND via 0 Ω and 47 kΩ resistor 5 µA
CI Input capacitance to ground (CANH or CANL) 25 pF
CID Differential input capacitance 14 pF
RID Differential input resistance TXD_INT = VCCINT, normal mode: -2.0 V ≤ VCANH ≤+7.0 V; -2.0 V ≤VCANL ≤ + 7.0 V 60 100
RIN Single ended Input resistance (CANH or CANL) -2.0 V ≤ VCANH ≤+7.0 V; -2.0 V ≤VCANL ≤ + 7.0 V 30 50
RIN(M) Input resistance matching: [1 – (RIN(CANH) / (RIN(CANL))] × 100% VCANH = VCANL = 5.0 V –1 1 %
VCCOUT SUPPLY TERMINAL
VCCOUT 5 V output supply ICCOUT = -70 mA to 0 mA; VSUP = 5.5 V to 18 V; -40°C < TA < 85°C 4.75 5 5.25 V
VDROP Drop out voltage VCCOUT = 5 V, VSUP = 12 V, ICCOUT = 70 mA 300 500 mV
ΔVCC(ΔVSUP) Line regulation VSUP = 5.5 V to 30 V, ΔVCCOUT, ICCOUT = 10 mA 50 mV
ΔVCC(ΔVSUPL) Load regulation VSUP = 14 V,   ICCOUT = 1 mA to 70 mA, ΔVCCOUT, –40℃ ≤ TA ≤ 125℃ 60 mV
UVCCOUT Under voltage threshold on VCCOUT 4.2 4.55 V
FLTR TERMINAL
VMEASURE Voltage measured at FLTR pin 1.5 V
C(FLTR) Filter pin capacitor External filter capacitor 300 330 nF
INH OUTPUT TERMINAL (HIGH VOLTAGE OUTPUT)
ΔVH High-level voltage drop INH with respect to VSUP IINH = - 0.5 mA 0.5 1 V
ILKG(INH) Leakage current INH = 0 V, Sleep Mode –0.5 0.7 µA
WAKE INPUT TERMINAL (HIGH VOLTAGE INPUT)
VIH High-level input voltage Standby mode, WAKE pin enabled VSUP–2 V
VIL Low-level input voltage Standby mode, WAKE pin enabled VSUP–3 V
IIH High-level input current WAKE = VSUP–1 V –25 –15 µA
IIL Low-level input current WAKE = 1 V 15 25 µA
tWAKE WAKE filter time Wake up filter time from a wake edge on WAKE; standby, sleep mode 50 µs
SDI, SCK, GPIO1 INPUT TERMINALS
VIH High-level input voltage 0.7 VIO
VIL Low-level input voltage 0.3 VIO
IIH High-level input leakage current Inputs = VIO = 5.25 V –1 1 µA
IIL Low-level input leakage current Inputs = 0 V, VIO = 5.25 V   –100 –5 µA
CIN Input capacitance 18 MHz 10 12 pF
ILKG(OFF) Unpowered leakage current (SDI and SCK only) Inputs = 5.25 V, VIO = VSUP = 0 V –1 1 µA
nCS INPUT TERMINAL
VIH High-level input voltage 0.7  VIO
VIL Low-level input voltage 0.3  VIO
IIH High-level input leakage current nCS = VIO = 5.25 V –1 1 µA
IIL Low-level input leakage current nCS = VIO = 5.25 V –50 –5 µA
ILKG(OFF) Unpowered leakage current nCS = 5.25 V, VIO = VSUP = 0 V –1 1 µA
RST INPUT TERMINAL
VIH High-level input voltage 0.7 VIO
VIL Low-level input voltage 0.3 VIO
IIH High-level input leakage current RST = VIO = 5.25 V 1 10 µA
IIL Low-level input leakage current RST = 0 V –1 1 µA
ILKG(OFF) Unpowered leakage current RST = VIO, VSUP = 0 V –7.5 7.5 µA
tPULSE_WIDTH Width of the input pulse 30 µs
SDO, GPIO1, GPO2 OUTPUT TERMINAL; nINT (OPEN DRAIIN) and nWKRQ (WHEN PROGRAMMED TO WORK OFF OF VIO AND IS OPEN DRAIN)
VOH High-level output voltage 0.8  VIO
VOL Low-level output voltage 0.2  VIO
nWKRQ OUTPUT TERMINAL (DEFAULT INTERNAL VOLTAGE RAIL)
VOH High-level output voltage Default value when based upon internal voltage rail 2.8 3.6 V
VOL Low-level output voltage Default value when based upon internal voltage rail 0.7 V
OSC1 TERMINAL AND CRYSTAL SPECIFICATION
VIH High-level input voltage 0.85 1.10 VIO
VIL Low-level input voltage 0.3 VIO
FOSC1 Clock-In frequency tolerance , see section Section 9.1.1   20 MHz –0.5 0.5 %
FOSC1 Clock-In frequency tolerance, see section Section 9.1.1 40 MHz –0.5 0.5 %
tDC Input duty cycle 45 55 %
ESR Crystal ESR for load capacitance (2) 60 Ω
All TXD_INT, RXD_INT and EN_INT references are for internal nodes that represent the same functions for a physical layer transceiver.
Specified by design