ZHCSJK5C January 2018 – October 2020 TCAN4550-Q1
The TCAN4550-Q1 supports dominant state timeout. This is an internal function based upon the TXD_INT path. The transceiver can be tested for this by placing the device into test mode and putting a dominant on the GPIO1 pin and monitor the GPO2 for RXD_INT_PHY. The TXD_INT DTO circuit prevents the local node from blocking network communication in the event of a hardware or software failure where TXD_INT is held dominant (low) longer than the timeout period tTXD_INT_DTO. The TXD_INT DTO circuit is triggered by a falling edge on TXD_INT. If no rising edge is seen before the timeout constant of the circuit, tTXD_INT_DTO, the CAN driver is disabled. This frees the bus for communication between other nodes on the network. The CAN driver is re-activated when a recessive signal (high) is seen on TXD_INT terminal, thus clearing the dominant timeout. The receiver remains active and the RXD_INT terminal reflects the activity on the CAN bus and the bus terminals is biased to recessive level during a TXD_INT DTO fault.
The minimum dominant TXD_INT time allowed by the TXD_INT DTO circuit limits the minimum possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD_INT) for the worst case, where five successive dominant bits are followed immediately by an error frame.