ZHCSJK5D January 2018 – June 2022 TCAN4550-Q1
This input pin is used to shift data into the device. Once the SPI is enabled by a low on nCS the SDI samples, the input shifted data on each rising edge of the SCLK. The data is shifted into a 32-bit shift register. If the command code was a write, the new data is written into the addressed register only after exactly 32 bits have been shifted in by SCLK and the nCS has a rising edge to deselect the device. If there are not exactly a multiple of 32 bits shifted in to the device, the during one SPI transaction (nCS low) the last word of the transfer is ignored, the SPIERR flag is set.
Due to needing multiples of 32 bits on each SPI transaction, the device should be wired for parallel operation of the SPI as a bus with control to the device via nCS and not as a daisy chain of shift registers.